公开(公告)号：US20060190685A1

公开(公告)日：2006-08-24

申请号：US11054182

申请日：2005-02-09

申请人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

发明人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F12/0837 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/1041 ,  G06F2212/683

摘要： A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

摘要翻译： 公开了一种使翻译控制条目（TCE）高速缓存内的条目无效的方法和装置。 主机桥耦合在一组处理器和一组适配器之间。 主机桥包括TCE缓存。 TCE缓存包含位于系统内存中的TCE表中最近使用的TCE的副本。 响应于一个处理器对TCE表中的TCE进行修改，将存储器映射的输入/输出（MMIO）存储发送到TCE无效寄存器，以指定修改的TCE的地址。 然后使用TCE无效寄存器内的数据来产生用于使包含TCE表中修改的TCE的未修改副本的TCE缓存中的条目无效的命令。 该命令随后发送到主机桥，使TCE缓存中的条目无效。

公开(公告)号：US20060179334A1

公开(公告)日：2006-08-10

申请号：US11054392

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

发明人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在用于操作DIMM和/或DRAM的预定/预设阈值功率/温度值以上的热点。 存储器控制器逻辑基于从特定DIMM / DRAM接收的反馈数据达到预设阈值功率使用值，来限制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20080028156A1

公开(公告)日：2008-01-31

申请号：US11836908

申请日：2007-08-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

公开(公告)号：US20060179248A1

公开(公告)日：2006-08-10

申请号：US11055640

申请日：2005-02-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

公开(公告)号：US20070073919A1

公开(公告)日：2007-03-29

申请号：US11226967

申请日：2005-09-15

申请人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。

公开(公告)号：US20060190636A1

公开(公告)日：2006-08-24

申请号：US11054183

申请日：2005-02-09

申请人： George Daly ,  James Fields

发明人： George Daly ,  James Fields

IPC分类号： G06F13/28

CPC分类号： G06F12/0835 ,  G06F13/28

摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

摘要翻译： 公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。 最初，外围设备发出多高速缓存行DMA请求。 多高速缓存行DMA请求被缓存内存窥探。 然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。 响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。

公开(公告)号：US20070143511A1

公开(公告)日：2007-06-21

申请号：US11304474

申请日：2005-12-15

申请人： George Daly ,  James Fields ,  Donald Grice ,  Thomas Heller ,  Appoloniel Tankeh

发明人： George Daly ,  James Fields ,  Donald Grice ,  Thomas Heller ,  Appoloniel Tankeh

IPC分类号： G06F13/00

CPC分类号： G06F13/4269

摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.

摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。

公开(公告)号：US20060179185A1

公开(公告)日：2006-08-10

申请号：US11054403

申请日：2005-02-09

申请人： George Daly ,  James Fields ,  Paul Umbarger ,  Kenneth Wright

发明人： George Daly ,  James Fields ,  Paul Umbarger ,  Kenneth Wright

IPC分类号： G06F3/06

CPC分类号： G06F13/28 ,  G06F12/0815 ,  G06F12/0897

摘要： A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

摘要翻译： 公开了一种用于在数据处理系统中处理写入请求的方法，系统和计算机程序产品。 该方法包括在互连总线上接收针对第一地址的第一写入请求，并且在互连总线上接收针对随后的第二地址的后续的第二写入请求。 随后的第二写请求在完成第一写请求之前完成，并且响应于在第一写请求完成之前接收到针对第二地址的读请求，与第二写请求的第二地址相关联的数据仅在 第一个写请求完成。

公开(公告)号：US20070088926A1

公开(公告)日：2007-04-19

申请号：US11250022

申请日：2005-10-13

申请人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

IPC分类号： G06F12/14

CPC分类号： G06F12/0831 ,  G06F12/0815 ,  G06F12/0824

摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.

摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控​​制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

公开(公告)号：US20060271741A1

公开(公告)日：2006-11-30

申请号：US11136642

申请日：2005-05-24

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

摘要翻译： 响应于程序代码的执行，用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。 响应于初始化，擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。 响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在 局部一致性域。