公开(公告)号：US07154724B2

公开(公告)日：2006-12-26

申请号：US10812378

申请日：2004-03-29

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H02H9/04 ,  H01L23/62

CPC classification number: H01L27/0262

Abstract: An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.

Abstract translation: 公开了具有改进的ESD保护的输入和输出（I / O）电路。 电路具有输出缓冲器，其具有耦合到PMOS晶体管的NMOS晶体管，ESD保护电路具有集成在其中并耦合到输出缓冲器的寄生可控硅整流器（SCR），以及二极管串，其具有预定数量的二极管 NMOS晶体管的源节点并接地，其中二极管串上的电压降增加了SCR栅极保持电压，从而为ESD保护电路设置ESD保护保持电压。

公开(公告)号：US20060157791A1

公开(公告)日：2006-07-20

申请号：US11037868

申请日：2005-01-18

Applicant: Jian-Hsing Lee ,  Fu-Liang Yang ,  Chien-Chao Huang

Inventor： Jian-Hsing Lee ,  Fu-Liang Yang ,  Chien-Chao Huang

IPC: H01L23/62

CPC classification number: H01L27/1203 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection device. A first-type well is formed on an insulating layer. First and second second-type doped regions are formed on the first-type well. A first body-tie region is formed on the first-type well and is connected to one side of the first and the second second-type doped regions. A polysilicon gate layer is formed on the first-type well and the body-tie region, and is located between the first and the second second-type doped regions. The first first-type doped region is connected to the first body-tie region. The second first-type doped region is formed on the first-type well.

Abstract translation: ESD保护装置。 在绝缘层上形成第一型阱。 第一和第二二次掺杂区形成在第一型阱上。 在第一类型阱上形成第一结扎区，并连接到第一和第二第二类型掺杂区的一侧。 多晶硅栅层形成在第一型阱和体结区上，位于第一和第二第二掺杂区之间。 第一第一掺杂区域连接到第一贴合区域。 在第一型阱上形成第二第一掺杂区。

公开(公告)号：US20060114629A1

公开(公告)日：2006-06-01

申请号：US11305983

申请日：2005-12-19

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

公开(公告)号：US20050254189A1

公开(公告)日：2005-11-17

申请号：US11091131

申请日：2005-03-28

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: G01R27/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/02 ,  H01L29/00 ,  H01L29/74 ,  H02H9/00

CPC classification number: H01L27/0262 ,  G11C17/16 ,  G11C17/18 ,  H01L29/7436

Abstract: An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

Abstract translation: ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。 具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。 可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。 在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

公开(公告)号：US20050237682A1

公开(公告)日：2005-10-27

申请号：US10831897

申请日：2004-04-26

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266

Abstract: A circuit and a method for solving the general problem of protecting core devices in integrated circuits from electrostatic discharge damage is provided. This circuit and a method prevents ESD voltage breakdown of thin oxide field effect transistors which are directly connected to the core Vdd power supply. The embodiments of this invention use inverter buffers using a thick or thin oxide devices at the input to the core circuitry is to be protected. Other embodiments of this invention use pass transistor or transfer gates made with thick or thin oxide devices at the input to the core circuitry is to be protected.

Abstract translation: 提供了解决集成电路中的核心器件保护静电放电损坏的一般问题的电路和方法。 该电路和方法防止直接连接到核心Vdd电源的薄氧化物场效应晶体管的ESD电压击穿。 使用在核心电路的输入端使用厚或薄的氧化物装置的逆变器缓冲器的保护。 本发明的其它实施例使用传输晶体管或由厚或薄的氧化物器件制成的传输栅极在核心电路的输入端被保护。

公开(公告)号：US06879203B2

公开(公告)日：2005-04-12

申请号：US10821270

申请日：2004-04-08

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract translation: 本发明提供了用于整个芯片静电放电，ECD，保护方案的两个电路实施例。 它还包括一个全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06803259B2

公开(公告)日：2004-10-12

申请号：US10404620

申请日：2003-03-31

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L21332

CPC classification number: H01L27/0262 ,  H01L29/74

Abstract: A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.

公开(公告)号：US06784498B1

公开(公告)日：2004-08-31

申请号：US10403976

申请日：2003-03-31

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu

IPC: H01L2362

CPC classification number: H01L27/0262 ,  H01L29/0692 ,  H01L29/87

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical.

Abstract translation: 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及第一和第二晶体管，以及阱中的第二导电类型的掺杂区域，其中第一和第二晶体管中的每一个的漏极和源极区域的剖面是不对称的。

公开(公告)号：US06756642B2

公开(公告)日：2004-06-29

申请号：US10291053

申请日：2002-11-07

Applicant: Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

Inventor： Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

IPC: H01L2362

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

Abstract translation: 在高电压n沟道MOS结构中，将p +扩散和n阱插入NMOS漏极区域，并通过形成寄生SCR提供ESD保护，允许使用5V信号，并将回跳电压降低到2V以下。

公开(公告)号：US06703663B1

公开(公告)日：2004-03-09

申请号：US09655086

申请日：2000-09-05

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

IPC: H01L2976

CPC classification number: H01L29/7833 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/1083

Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Abstract translation: 用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。 在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。 在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。 在栅极堆叠的侧壁上形成间隔物。 然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。 形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。