公开(公告)号：US06756642B2

公开(公告)日：2004-06-29

申请号：US10291053

申请日：2002-11-07

申请人： Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

发明人： Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

摘要翻译： 在高电压n沟道MOS结构中，将p +扩散和n阱插入NMOS漏极区域，并通过形成寄生SCR提供ESD保护，允许使用5V信号，并将回跳电压降低到2V以下。

公开(公告)号：US06762439B1

公开(公告)日：2004-07-13

申请号：US09898386

申请日：2001-07-05

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Ta-Lee Yu

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Ta-Lee Yu

IPC分类号： H01L2974

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.

摘要翻译： 实现了新的静电放电保护装置。 p阱区位于半导体衬底中。 p阱区域中的n +区域连接到第一电压源。 p阱区域中的n阱区域与n +区域间隔开，使得在正常操作期间耗尽区域将在其间延伸。 在正常操作期间，n阱区域中的p +区域连接到比第一电压源更大的值的第二电压源。 在静电放电事件期间，电流通过n +区域传导到p +区域。

公开(公告)号：US20080128818A1

公开(公告)日：2008-06-05

申请号：US11606424

申请日：2006-11-30

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC分类号： H01L27/06

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

公开(公告)号：US07256975B2

公开(公告)日：2007-08-14

申请号：US10867112

申请日：2004-06-14

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H02H9/00

CPC分类号： H03K17/08142 ,  H01L27/0266

摘要： An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

摘要翻译： 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。

公开(公告)号：US06614693B1

公开(公告)日：2003-09-02

申请号：US10100752

申请日：2002-03-19

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/16

摘要： A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

摘要翻译： 从闪存EEPROM擦除数据的组合擦除方法消除了在快速EEPROM的隧道氧化物中捕获的电荷，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的第一实施例方法是通过负栅极擦除开始，以从浮置栅极去除电荷，随后进行源擦除以进一步从浮置栅极去除电荷，最后再进行通道擦除以去除电荷。 第二实施例开始于负栅极擦除，其具有电压的增量步进以从浮置栅极去除电荷。 之后是源擦除来去除EEPROM单元的隧道氧化物。 第三实施例开始于具有逐渐增加的步进电压以从浮动栅极去除电荷的源擦除。 之后是通道擦除以去除EEPROM单元的隧穿氧化物。

公开(公告)号：US06552372B2

公开(公告)日：2003-04-22

申请号：US09827194

申请日：2001-04-05

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

IPC分类号： H01L2972

CPC分类号： H01L27/0251

摘要： An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

摘要翻译： 诸如输入 - 输出缓冲器的MOS集成电路通过平衡通过驱动器的有源和非有效部分的ESD电流来改善对静电放电（ESD）的损坏。 通过增加限定有源部分中的驱动器的栅极的半导体材料的多指通道的宽度和长度来实现ESD电流的更好的平衡。 有源部分的驱动器较长的栅极增加了其承载电流的能力，从而导致有源和非活动部分之间的ESD电流分布更为对称，而不会降低IC的正常性能。

公开(公告)号：US06541824B2

公开(公告)日：2003-04-01

申请号：US09957275

申请日：2001-09-21

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0277 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.

公开(公告)号：US06362035B1

公开(公告)日：2002-03-26

申请号：US09498741

申请日：2000-02-07

申请人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

IPC分类号： H01L2144

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  Y10S438/919

摘要： A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

摘要翻译： 描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。 通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。 随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。 在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。 该方法在利用浅沟槽隔离的工艺中示出并且特别有效。

公开(公告)号：US06190954B1

公开(公告)日：2001-02-20

申请号：US09229381

申请日：1999-01-11

申请人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

发明人： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

IPC分类号： H01L218238

CPC分类号： H01L21/823892 ,  H01L27/0921

摘要： A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

摘要翻译： 公开了一种通过增加存在于CMOS结构中的寄生npn和pnp晶体管的跳转电压VBO或触发点来提供更稳健的闭锁免疫CMOS晶体管的方法。 这些目标已经通过在双井CMOS结构的n阱和p阱两者中添加阻挡层来实现，从而分别增加了寄生npn和pnp晶体管的电子和空穴的能隙。

公开(公告)号：US06992361B2

公开(公告)日：2006-01-31

申请号：US10761658

申请日：2004-01-20

申请人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L29/00

CPC分类号： H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

摘要： A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

摘要翻译： CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。