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公开(公告)号：US08551833B2
公开(公告)日：2013-10-08
申请号：US13161013
申请日：2011-06-15
IPC分类号： H01L21/8238
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/78696
摘要： A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device.
摘要翻译： 示出了一种堆叠的平面器件及其形成方法，其包括在衬底上形成具有交替的牺牲层和沟道层的层叠层，图案化堆叠，使得堆叠的侧面包括牺牲层和沟道层的暴露表面， 在堆叠的区域上形成虚拟栅极结构以建立平坦区域，在虚拟栅极结构周围形成介电层以覆盖与平面区域相邻的区域，去除伪栅极结构以暴露堆叠，选择性地将堆叠蚀刻到 从平面区域中的沟道层去除牺牲层，以及在沟道层之间和之间形成栅极导体以形成晶体管器件。
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公开(公告)号：US20130175624A1
公开(公告)日：2013-07-11
申请号：US13611335
申请日：2012-09-12
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
摘要翻译： 半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分 蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。
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公开(公告)号：US08466012B1
公开(公告)日：2013-06-18
申请号：US13364036
申请日：2012-02-01
IPC分类号： H01L21/00
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1207 , H01L27/1211
摘要： Hybrid bulk finFET and SOI finFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having SOI finFET and bulk finFET devices includes the following steps. A wafer is provided having an active layer separated from a substrate by a BOX. Portions of the active layer and BOX are removed in a second region of the wafer so as to expose the substrate. An epitaxial material is grown in the second region of the wafer templated from the substrate. Fins are etched in the active layer and in the epitaxial material using fin lithography hardmasks. Gate stacks are formed covering portions of the fins which serve as channel regions of the SOI finFET/bulk finFET devices. An epitaxial material is grown on exposed portions of the fins which serves as source and drain regions of the SOI finFET/bulk finFET devices.
摘要翻译： 提供了混合体finFET和SOI finFET器件及其制造方法。 在一个方面，一种制造具有SOI finFET和bulk finFET器件的CMOS电路的方法包括以下步骤。 提供具有通过BOX从衬底分离的活性层的晶片。 有源层和BOX的部分在晶片的第二区域中被去除，以便露出衬底。 在从衬底模板化的晶片的第二区域中生长外延材料。 使用翅片光刻硬掩模在有源层和外延材料中蚀刻金箔。 形成覆盖作为SOI finFET /体鳍片FET器件的沟道区域的鳍片的部分的栅极叠层。 在作为SOI finFET /体鳍片FET器件的源极和漏极区域的鳍片的暴露部分上生长外延材料。
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公开(公告)号：US20120319178A1
公开(公告)日：2012-12-20
申请号：US13161013
申请日：2011-06-15
IPC分类号： H01L21/335 , H01L29/80 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/78696
摘要： A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device.
摘要翻译： 示出了一种堆叠的平面器件及其形成方法，其包括在衬底上形成具有交替的牺牲层和沟道层的层叠层，图案化堆叠，使得堆叠的侧面包括牺牲层和沟道层的暴露表面， 在堆叠的区域上形成虚拟栅极结构以建立平坦区域，在虚拟栅极结构周围形成介电层以覆盖与平面区域相邻的区域，去除伪栅极结构以暴露堆叠，选择性地将堆叠蚀刻到 从平面区域中的沟道层去除牺牲层，以及在沟道层之间和之间形成栅极导体以形成晶体管器件。
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公开(公告)号：US20110233674A1
公开(公告)日：2011-09-29
申请号：US12748761
申请日：2010-03-29
IPC分类号： H01L29/786 , H01L21/336 , G06F17/50
CPC分类号： G06F17/5068 , H01L21/26586 , H01L21/823412 , H01L21/823807 , H01L27/0207 , H01L27/1203 , H01L29/42384 , H01L29/66537 , H01L29/78612
摘要： A semiconductor structure, and a method of making, includes: a substrate; and at least one layer of silicon overlying the substrate, the layer of silicon including at least one active region having at least one device, a design layout of the active region in accordance with design layout rules including: a multiple-fingered device is mapped to a symmetric device or an asymmetric body-tied device; a single-fingered device is mapped to an asymmetric device; an active region having a single-fingered device is entirely source-up or source-down; and an active region falls into one of two categories: the active region does not include any symmetric devices or the active region does not include any asymmetric devices. In another exemplary embodiment, a design structure tangibly embodied on a computer readable medium, for use by a machine in the design, manufacture or simulation of an integrated circuit having the above semiconductor structure.
摘要翻译： 半导体结构及其制造方法包括：基板; 以及覆盖所述衬底的至少一层硅，所述硅层包括具有至少一个器件的至少一个有源区，所述有源区的设计布局根据设计布局规则包括：多指器件被映射到 对称装置或不对称的身体绑定装置; 单指装置被映射到非对称装置; 具有单指装置的有源区域完全是源极或源极; 并且有源区域属于两个类别之一：有源区域不包括任何对称设备，或者有源区域不包括任何非对称设备。 在另一个示例性实施例中，设计结构有形地体现在计算机可读介质上，供机器在设计，制造或模拟具有上述半导体结构的集成电路中使用。
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公开(公告)号：US20110063019A1
公开(公告)日：2011-03-17
申请号：US12561880
申请日：2009-09-17
IPC分类号： G05F3/02 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt1, and the gate electrode and the second dielectric layer form a third gate having a threshold voltage Vt2 different than Vt1.
摘要翻译： 公开了双电介质三栅场效应晶体管，制造双电介质三栅场效应晶体管的方法，以及操作双电介质三栅效应晶体管的方法。 在一个实施例中，双电介质三栅晶体管包括衬底，衬底上的绝缘层和至少一个半导体鳍片。 具有第一介电常数的第一电介质在翅片的侧壁上延伸，并且金属层在第一电介质上延伸，并且具有第二介电常数的第二电介质位于散热片的顶表面上。 栅电极在鳍片和第一和第二电介质上延伸。 栅电极和第一电介质层形成具有阈值电压Vt1的第一栅极和第二栅极，栅电极和第二电介质层形成具有不同于Vt1的阈值电压Vt2的第三栅极。
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公开(公告)号：US20130176769A1
公开(公告)日：2013-07-11
申请号：US13345619
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C11/417 , G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
摘要翻译： 一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。
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公开(公告)号：US20130176771A1
公开(公告)日：2013-07-11
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极 线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。
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49.发明授权公开(公告)号：US08619465B2
公开(公告)日：2013-12-31
申请号：US13345629
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置中的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到写入位线的每个通过栅极晶体管的源极或漏极; 导通栅极和下拉晶体管的共用源极/漏极端子处的内部结二极管，用于阻止从写位线到电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。
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50.发明授权公开(公告)号：US08597991B2
公开(公告)日：2013-12-03
申请号：US13568689
申请日：2012-08-07
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/8238 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
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