公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

申请人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

摘要： A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US06248673B1

公开(公告)日：2001-06-19

申请号：US09511334

申请日：2000-02-23

申请人： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

发明人： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

IPC分类号： H01L21469

CPC分类号： H01L29/518 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31629 ,  H01L21/324 ,  Y10S438/958

摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device. The method is a “pure H2 (100%)” alloy recipe to use after contact opening or metal-1 formation.

摘要翻译： 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成微电子器件。 然后在微电子器件上形成由钝化介电材料形成的钝化介电层，该钝化介电材料选自氟硅酸盐玻璃（FSG）钝化介电材料，大气压化学气相沉积（APCVD）钝化介电材料，低于大气压的化学气相沉积 （SACVD）钝化介电材料和旋涂玻璃（SOG）钝化介电材料以从微电子器件形成钝化的微电子器件。 最后，在使用采用包含氢的气氛的热退火方法的同时进行退火，该钝化微电子器件形成稳定的钝化微电子器件。 该方法是在接触开口或金属-1形成之后使用的“纯H 2（100％）”合金配方。

公开(公告)号：US6046062A

公开(公告)日：2000-04-04

申请号：US373246

申请日：1999-08-12

申请人： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

发明人： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14

摘要： This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

摘要翻译： 本发明涉及集成电路器件的特性，更具体地说，涉及一种用于在FET器件的阈值电压特性中监测不可接受的扭结行为的改进方法，这可能是由于栅极氧化物厚度减小和衬底掺杂浓度降低引起的 沿着由STI界定的频道区域的长度。 这是通过将一对漏极电流与栅极电压特性作为衬底电压的两个值的函数来实现的。 在两个曲线之间的相对电压偏移在远低于扭结的漏极电流的值处以及远远高于扭结的漏极电流的值进行比较。 扭结行为的定量程度由对应于远低于扭结的漏极电流值的电压偏移量超过相应于低于扭结线圈的漏极电流的值的电压偏移量来确定多大。