公开(公告)号：US5546552A

公开(公告)日：1996-08-13

申请号：US440225

申请日：1995-05-12

申请人： Brett Coon ,  Yoshiyuki Miyayama ,  Le T. Nguyen ,  Johannes Wang

发明人： Brett Coon ,  Yoshiyuki Miyayama ,  Le T. Nguyen ,  Johannes Wang

IPC分类号： C10G1/00 ,  C10G17/02 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/76 ,  G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30101 ,  C10G1/00 ,  C10G17/02 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

摘要翻译： 一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。 系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。 然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。 下一个指令检测器基于所述指令字节集来确定第一指令的结束。 提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。 然后对复杂指令流中的剩余指令字节重复该过程。 孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

公开(公告)号：US5987593A

公开(公告)日：1999-11-16

申请号：US962705

申请日：1997-11-03

申请人： Cheryl D. Senter ,  Johannes Wang ,  Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen

发明人： Cheryl D. Senter ,  Johannes Wang ,  Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F9/44 ,  G06F9/445 ,  G06F9/455

CPC分类号： G06F9/3826 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3853

摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load/store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

摘要翻译： 本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。 为了执行此任务，提供了一个加载/存储单元，其主要目的是使可能的负载请求无序地尽可能快地获得负载数据以供指令执行单元使用。 如果没有地址冲突，没有写入，只能执行加载操作。 当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。 写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。 数据高速缓存单元返回8字节的未对齐数据。 加载/存储单元在返回指令执行单元之前将其正确对齐。 因此，加载/存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

公开(公告)号：US5438668A

公开(公告)日：1995-08-01

申请号：US857599

申请日：1992-03-31

申请人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

发明人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

IPC分类号： C10G1/00 ,  C10G17/02 ,  G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/76 ,  G06F9/312 ,  G06F9/315

CPC分类号： G06F9/30101 ,  C10G1/00 ,  C10G17/02 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

摘要翻译： 一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。 系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。 然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。 下一个指令检测器基于所述指令字节集来确定第一指令的结束。 提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。 然后对复杂指令流中的剩余指令字节重复该过程。 孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

公开(公告)号：US07664935B2

公开(公告)日：2010-02-16

申请号：US12046318

申请日：2008-03-11

申请人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

发明人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

摘要翻译： 一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。 系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。 然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。 下一个指令检测器基于所述指令字节集来确定第一指令的结束。 提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。 然后对复杂指令流中的剩余指令字节重复该过程。 孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

公开(公告)号：US07343473B2

公开(公告)日：2008-03-11

申请号：US11167289

申请日：2005-06-28

申请人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

发明人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

IPC分类号： G06F9/30

CPC分类号： G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

摘要翻译： 一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。 系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。 然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。 下一个指令检测器基于所述指令字节集来确定第一指令的结束。 提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。 然后对复杂指令流中的剩余指令字节重复该过程。 孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

公开(公告)号：US06263423B1

公开(公告)日：2001-07-17

申请号：US09401860

申请日：1999-09-22

申请人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

发明人： Brett Coon ,  Yoshiyuki Miyayama ,  Le Trong Nguyen ,  Johannes Wang

IPC分类号： G06F930

CPC分类号： G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853

摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

摘要翻译： 一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。 系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。 然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。 下一个指令检测器基于所述指令字节集来确定第一指令的结束。 提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。 然后对复杂指令流中的剩余指令字节重复该过程。 孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

公开(公告)号：US06922795B2

公开(公告)日：2005-07-26

申请号：US10700621

申请日：2003-11-05

申请人： Yoshiyuki Miyayama ,  Makoto Kudo ,  Yoichi Hijikata

发明人： Yoshiyuki Miyayama ,  Makoto Kudo ,  Yoichi Hijikata

IPC分类号： G06F11/22 ,  G06F11/28 ,  G06F11/36 ,  G06F15/78 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F2201/88

摘要： The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].

摘要翻译： 本发明提供一种微型计算机，其能够使用少量终端在大规模生产的芯片上实现实时跟踪，从指定范围内获取跟踪信息，并且与电子设备一起测量执行时间，以及包括 这台微机。 跟踪信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。 当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。 微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。 调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

公开(公告)号：US20050102579A1

公开(公告)日：2005-05-12

申请号：US10985901

申请日：2004-11-12

申请人： Yoshiyuki Miyayama ,  Makoto Kudo ,  Yoichi Hijikata

发明人： Yoshiyuki Miyayama ,  Makoto Kudo ,  Yoichi Hijikata

IPC分类号： G06F11/22 ,  G06F11/28 ,  G06F11/36 ,  G06F15/78 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F2201/88

摘要： The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].

摘要翻译： 本发明提供一种微型计算机，其能够使用少量终端在大规模生产的芯片上实现实时跟踪，从指定范围内获取跟踪信息，并且与电子设备一起测量执行时间，以及包括 这台微机。 跟踪信息输出部分（16）将用于实现实时跟踪的跟踪信息输出到四个专用终端。 当PC绝对分支发生时，将CPU的指令执行状态信息（DST [2：0]）输出到三个终端和分支目的地的PC值（DPCO），串行连接到一个终端。 微型计算机（10）以规定的顺序向DST [2]输出指示轨迹范围或执行时间测量范围的开始和结束的信息。 调试工具（20）根据DST [2]中的值确定跟踪范围或执行时间测量范围的开始和结束。

公开(公告)号：US06560692B1

公开(公告)日：2003-05-06

申请号：US08859490

申请日：1997-05-20

申请人： Makoto Kudo ,  Satoshi Kubota ,  Yoshiyuki Miyayama ,  Hisao Sato

发明人： Makoto Kudo ,  Satoshi Kubota ,  Yoshiyuki Miyayama ,  Hisao Sato

IPC分类号： G06F1500

CPC分类号： G06F9/3004 ,  G06F9/30101 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/324 ,  G06F9/355

摘要： The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses. This group of dedicated stack pointer instructions comprises SP-relative load instructions, stack pointer move instructions, a call instruction, a ret instruction, a sequential push instruction, and a sequential pop instruction.

摘要翻译： 本发明的数据处理电路能够使用简单的指令有效地描述和执行作用于堆栈指针的进程。 它还能够有效地描述保存和恢复寄存器内容的进程，提高处理中断和子程序调用和返回的速度。 使用该数据处理电路的CPU包括专用堆栈指针寄存器SP，并且使用指令解码器将指定SP的一组专用堆栈指针指令解码为隐式操作数。 该组专用堆栈指针指令通过使用通用寄存器，PC，SP，地址加法器，ALU，PC增量器，内部总线，内部信号线和外部总线在硬件中实现。 该组专用堆栈指针指令包括SP相对负载指令，堆栈指针移动指令，调用指令，ret指令，顺序推送指令和顺序pop指令。

公开(公告)号：US06233596B1

公开(公告)日：2001-05-15

申请号：US09066348

申请日：1998-06-05

申请人： Satoshi Kubota ,  Makoto Kudo ,  Yoshiyuki Miyayama

发明人： Satoshi Kubota ,  Makoto Kudo ,  Yoshiyuki Miyayama

IPC分类号： G06F9302

CPC分类号： G06F9/30014 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/325 ,  G06F17/10

摘要： An objective of this invention is a design that improves the memory usage ratio and execution speed of a sum-of-products operation instruction, improves the critical path of sum-of-products operations, and prevents overflows. A sum-of-products operation circuit executes sum-of-products operations a number of times that is specified by number-of-executions information comprised within a sum-of-products operation instruction, under the control of a control circuit. The number of times the sum-of-products operation is to be executed is set into a register, that number is decremented every time one cycle of the sum-of-products operation ends, and the sum-of-products operation instruction ends when the value in the register reaches zero. If an interrupt is received during the execution of a plurality of sum-of-products operations, execution of the sum-of-products operations resumes after the interrupt processing. First and second sum-of-products input data are read at the same time by a single memory access. A 16-bit×16-bit multiplication result is added by a 32-bit adder, and upper 32-bit data is either incremented or decremented when a carry or borrow is generated by a lower 32-bit add.

摘要翻译： 本发明的目的是提高产品总和操作指令的存储器使用率和执行速度的设计，改善产品总和操作的关键路径，并防止溢出。 产品总和运算电路在控制电路的控制下，对包含在产品总和运算指令内的执行次数信息指定的次数进行乘积运算。 要执行产品总和操作的次数被设置为寄存器，每当产品总和操作的一个周期结束时，该数量减少，并且产品总和操作指令结束时 寄存器中的值达到零。 如果在执行多个产品总和操作期间接收到中断，则在中断处理之后恢复产品总和操作的执行。 通过单个存储器访问同时读取第一和第二产品总和输入数据。 一个16位×16位相乘结果由32位加法器相加，当32位加法器产生进位或借位时，高位32位数据被递增或递减。