公开(公告)号：US09460928B2

公开(公告)日：2016-10-04

申请号：US14612359

申请日：2015-02-03

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Han Chou ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/70 ,  H01L21/265 ,  H01L21/66 ,  H01L29/167 ,  H01L27/115 ,  H01L21/8232

CPC classification number: H01L21/26586 ,  H01L21/8232 ,  H01L22/12 ,  H01L22/20 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract translation: 半导体器件制造方法包括制备具有形成在基板上的突起的晶片。 所述突出部从所述基板的表面向上突出，并且具有从所述基板的表面测量的高度。 该方法还包括确定表示相邻投影之间的间隔的分布的间隔分布，并基于高度和间隔分布计算植入角度。 注入角度是基板的法线方向与注入方向之间的角度。 该方法还包括以所计算的植入角度注入离子。

公开(公告)号：US20150194808A1

公开(公告)日：2015-07-09

申请号：US14272115

申请日：2014-05-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Yu Wang ,  Tao-Cheng Lu ,  Yao-Wen Chang

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0259

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract translation: 提供一种包括PNP晶体管，保护电路和调整电路的静电放电保护装置。 PNP晶体管的发射极电连接到焊盘，并且PNP晶体管的集电极电连接到地。 保护电路电连接在PNP晶体管的基极与地之间，并提供放电路径。 当在焊盘上发生静电信号时，静电信号通过放电路径和PNP晶体管传导到地面。 调节电路电连接在PNP晶体管的发射极和基极之间。 当向焊盘提供电源电压时，调节电路根据电源电压向PNP晶体管的基极提供控制电压，以防止PNP晶体管的发射极和基极正向偏置。

公开(公告)号：US08937347B2

公开(公告)日：2015-01-20

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/4763 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

公开(公告)号：US20140231900A1

公开(公告)日：2014-08-21

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。