-
公开(公告)号：US20180159531A1
公开(公告)日：2018-06-07
申请号：US15371285
申请日：2016-12-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ming-Yin Lee , Wen-Tsung Huang , Shih-Yu Wang
IPC: H03K17/687 , H01L27/092 , H01L27/06 , H01L27/02
CPC classification number: H03K17/6872 , H01L27/0266 , H01L27/0629 , H01L27/0928
Abstract: A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.
-
公开(公告)号：US20170010321A1
公开(公告)日：2017-01-12
申请号：US14792148
申请日：2015-07-06
Applicant: MACRONIX International Co., Ltd.
Inventor： Shih-Yu Wang , Yao-Wen Chang , Tao-Cheng Lu
IPC: G01R31/28
CPC classification number: G01R31/2853 , G01R1/0491 , G01R31/3004
Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.
Abstract translation: 提供了锁存测试装置和方法，该方法包括以下步骤。 执行设定操作，根据测试范围设置基本测试值，并通过基本测试值设置触发脉冲和预定误差值。 通过触发脉冲进行被测晶片中的测试芯片的测试，并确定测试芯片是否处于闭锁状态。 根据确定结果，闩锁阈值和基本测试值来确定是否更新测试范围和锁存阈值以及是否返回到执行设置操作的步骤。 当测试芯片处于闩锁状态并且闩锁阈值和基本测试值之间的差异不大于预定误差值时，测试芯片上的测试被停止。
-
公开(公告)号：US10084449B2
公开(公告)日：2018-09-25
申请号：US15371285
申请日：2016-12-07
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ming-Yin Lee , Wen-Tsung Huang , Shih-Yu Wang
IPC: H01L27/02 , H03K17/687 , H01L27/092 , H01L27/06
CPC classification number: H03K17/6872 , H01L27/0262 , H01L27/0266
Abstract: A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.
-
公开(公告)号：US11817449B2
公开(公告)日：2023-11-14
申请号：US17244343
申请日：2021-04-29
Applicant: Macronix International Co., Ltd.
Inventor： Jung Chuan Ting , Shih-Yu Wang , Shao-Chi Chen
CPC classification number: H01L27/0292 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.
-
公开(公告)号：US11482520B2
公开(公告)日：2022-10-25
申请号：US16840489
申请日：2020-04-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shih-Yu Wang , Wen-Tsung Huang , Chih-Wei Hsu
IPC: H01L27/02
Abstract: The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.
-
Patent Agency Ranking
公开(公告)号：US10181466B2
公开(公告)日：2019-01-15
申请号：US15084557
申请日：2016-03-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Shih-Yu Wang , Ming-Yin Lee , Wen-Tsung Huang
Abstract: An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.
-
公开(公告)号：US20180374838A1
公开(公告)日：2018-12-27
申请号：US15631141
申请日：2017-06-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wen-Tsung Huang , Ming-Yin Lee , Shih-Yu Wang
Abstract: A semiconductor structure comprises a transistor. The transistor comprises a semiconductor substrate, a first source/drain side doped region, a second source/drain side doped region and a gate structure. The first source/drain side doped region comprises a lower doped portion having a conductivity type opposing to a conductivity type of the semiconductor substrate. The second source/drain side doped region comprises a first doped portion extended downward from an upper surface of the semiconductor substrate. The second source/drain side doped region has a bottom PN junction with the semiconductor substrate. The lower doped portion has a bottom surface below the bottom PN junction. A dopant concentration of the first doped portion is larger than a dopant concentration of the lower doped portion having the same conductivity type with the first doped portion.
-
公开(公告)号：US09625520B2
公开(公告)日：2017-04-18
申请号：US14792148
申请日：2015-07-06
Applicant: MACRONIX International Co., Ltd.
Inventor： Shih-Yu Wang , Yao-Wen Chang , Tao-Cheng Lu
CPC classification number: G01R31/2853 , G01R1/0491 , G01R31/3004
Abstract: Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip in a wafer under test is performed by the trigger pulse, and whether the test chip is in a latch-up state is determined. Whether to update a test range and a latch-up threshold value and whether to return to the step of performing the set operation are determined according to a determination result, the latch-up threshold value and the basic test value. When the test chip is in the latch-up state and a difference between the latch-up threshold value and the basic test value is not greater than the predetermined error value, the test on the test chip is stopped.
-
公开(公告)号：US20150194808A1
公开(公告)日：2015-07-09
申请号：US14272115
申请日：2014-05-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Shih-Yu Wang , Tao-Cheng Lu , Yao-Wen Chang
CPC classification number: H02H9/046 , H01L27/0259
Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.
Abstract translation: 提供一种包括PNP晶体管，保护电路和调整电路的静电放电保护装置。 PNP晶体管的发射极电连接到焊盘，并且PNP晶体管的集电极电连接到地。 保护电路电连接在PNP晶体管的基极与地之间，并提供放电路径。 当在焊盘上发生静电信号时，静电信号通过放电路径和PNP晶体管传导到地面。 调节电路电连接在PNP晶体管的发射极和基极之间。 当向焊盘提供电源电压时，调节电路根据电源电压向PNP晶体管的基极提供控制电压，以防止PNP晶体管的发射极和基极正向偏置。
-
公开(公告)号：US11837600B2
公开(公告)日：2023-12-05
申请号：US17526014
申请日：2021-11-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wen-Tsung Huang , Shih-Yu Wang , Chih-Wei Hsu
CPC classification number: H01L27/0262 , H01L29/7436
Abstract: The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.018 seconds)
