公开(公告)号：US20250056816A1

公开(公告)日：2025-02-13

申请号：US18780515

申请日：2024-07-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang ,  Hsing-Wen Chang ,  Yao-Wen Chang

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

公开(公告)号：US20160133718A1

公开(公告)日：2016-05-12

申请号：US14539768

申请日：2014-11-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.

Abstract translation: 提供一种半导体器件。 两个堆叠层设置在第一导电类型的衬底上。 每个堆叠层包括电介质层和导电层。 电介质层设置在基板上。 导电层设置在电介质层上。 第二导电类型的第一掺杂区具有第一掺杂剂并且被布置在堆叠层之间的衬底中。 在第一掺杂区域中设置预非晶化注入（PAI）区域。 第二导电类型的第二掺杂区域具有第二掺杂剂并且被布置在PAI区域中。 第一导电类型与第二导电类型不同。 第二掺杂剂的扩散速度比第一掺杂剂的扩散速度快，并且第二掺杂剂的热激活高于第一掺杂剂的扩散速率。

公开(公告)号：US20150200306A1

公开(公告)日：2015-07-16

申请号：US14154991

申请日：2014-01-14

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: H01L29/792 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833

Abstract: A non-volatile memory includes a substrate, a charge trapping structure disposed on the substrate, a buffer layer disposed on the charge trapping structure, and a plurality of conductive layers disposed on the buffer layer.

Abstract translation: 非易失性存储器包括衬底，设置在衬底上的电荷俘获结构，设置在电荷俘获结构上的缓冲层和设置在缓冲层上的多个导电层。

公开(公告)号：US08748963B1

公开(公告)日：2014-06-10

申请号：US13707426

申请日：2012-12-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/4763

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括设置在衬底上的栅极结构，掺杂区域，电荷存储层和第一介电层。 栅极结构两侧的基板上有凹槽。 栅极结构包括设置在衬底上的栅极电介质层和设置在栅极介电层上的栅极。 在栅介电层和衬底之间存在界面。 掺杂区域围绕凹部设置在基板中。 电荷存储层设置在凹部中，并且每个电荷存储层的顶表面高于界面。 第一介电层设置在电荷存储层与基板之间，电荷存储层与栅极结构之间。

公开(公告)号：US20240243180A1

公开(公告)日：2024-07-18

申请号：US18153368

申请日：2023-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： I-Chen Yang ,  Chun Liang Lu ,  Yung-Hsiang Chen ,  Yao-Wen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/66598

Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

公开(公告)号：US20190035930A1

公开(公告)日：2019-01-31

申请号：US15664010

申请日：2017-07-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/266

Abstract: A semiconductor structure includes a substrate, a first source/drain region, a second source/drain region, a channel doping region and a gate structure. The first source/drain region is disposed in the substrate. The first source/drain region includes a first region and a second region under the first region. The second source/drain region is disposed in the substrate. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed in the substrate between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. In a projection plane parallel to the top surface of the substrate, the second region of the first source/drain region is separated from the gate structure. The first source/drain region, the second source/drain region and the channel doping region have the same conductive type.

公开(公告)号：US09460928B2

公开(公告)日：2016-10-04

申请号：US14612359

申请日：2015-02-03

Applicant: Macronix International Co., Ltd.

Inventor： Chen-Han Chou ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/70 ,  H01L21/265 ,  H01L21/66 ,  H01L29/167 ,  H01L27/115 ,  H01L21/8232

CPC classification number: H01L21/26586 ,  H01L21/8232 ,  H01L22/12 ,  H01L22/20 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833

Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.

Abstract translation: 半导体器件制造方法包括制备具有形成在基板上的突起的晶片。 所述突出部从所述基板的表面向上突出，并且具有从所述基板的表面测量的高度。 该方法还包括确定表示相邻投影之间的间隔的分布的间隔分布，并基于高度和间隔分布计算植入角度。 注入角度是基板的法线方向与注入方向之间的角度。 该方法还包括以所计算的植入角度注入离子。

公开(公告)号：US08937347B2

公开(公告)日：2015-01-20

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L21/4763 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

公开(公告)号：US20140231900A1

公开(公告)日：2014-08-21

申请号：US14266079

申请日：2014-04-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L29/42352 ,  H01L29/66833

Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.

Abstract translation: 提供非易失性存储器。 非易失性存储器包括氧化物和多晶硅堆叠结构和电荷存储层。 氧化物和多晶硅堆叠结构设置在基板上。 在氧化物和多晶硅堆叠结构两侧的衬底中有凹槽。 氧化物和多晶硅堆叠结构包括氧化物层和多晶硅层。 氧化物层设置在衬底上，其中在氧化物层和衬底之间存在界面。 多晶硅层设置在氧化物层上。 电荷存储层设置在凹槽中并延伸到氧化物和多晶硅堆叠结构的侧壁，并且每个电荷存储层的顶表面高于界面。

公开(公告)号：US12176058B2

公开(公告)日：2024-12-24

申请号：US17953094

申请日：2022-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  I-Chen Yang

IPC: G11C16/14 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C16/16

Abstract: A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.