公开(公告)号：US20230065783A1

公开(公告)日：2023-03-02

申请号：US17647944

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

IPC: G06F3/06

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

公开(公告)号：US20220392509A1

公开(公告)日：2022-12-08

申请号：US17846751

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：US20220138102A1

公开(公告)日：2022-05-05

申请号：US17573938

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/38 ,  G06F11/14 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US20220068264A1

公开(公告)日：2022-03-03

申请号：US17006157

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G10L15/16 ,  G10L15/30 ,  G10L15/22 ,  G06N3/08 ,  G06F16/635

Abstract: Systems and methods for distributing cloud-based language processing services to partially execute in a local device to reduce latency perceived by the user. For example, a local device may receive a request via audio input, that requires a cloud-based service to process the request and generate a response. A partial response may be generated locally and played back while a more complete response is generated remotely.

公开(公告)号：US11199995B2

公开(公告)日：2021-12-14

申请号：US16688250

申请日：2019-11-19

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F12/0873 ,  G06F11/07

Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory subsystem can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

公开(公告)号：US11061819B2

公开(公告)日：2021-07-13

申请号：US16424424

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L29/08 ,  H04W84/04

Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US20210072986A1

公开(公告)日：2021-03-11

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G11C7/06 ,  G11C7/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US20210056350A1

公开(公告)日：2021-02-25

申请号：US16545854

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Hongyu Wang ,  Sean Stephen Eilert

IPC: G06K9/62 ,  G06N3/08 ,  G06F13/16

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN) as well as different versions of a feature dictionary. In the system, encoded inputs for the ANN can be decoded by the feature dictionary, which allows for encoded input to be sent to a master version of the ANN over a network instead of an original version of the input which usually includes more data than the encoded input. Thus, by using the feature dictionary for training of a master ANN there can be reduction of data transmission.

公开(公告)号：US10922020B2

公开(公告)日：2021-02-16

申请号：US16382511

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US20200382590A1

公开(公告)日：2020-12-03

申请号：US16424411

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: H04L29/08 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/02

Abstract: Systems, methods and apparatuses to provide memory as a service are described. For example, a borrower device is configured to: communicate with a lender device; borrow an amount of memory from the lender device; expand memory capacity of the borrower device for applications running on the borrower device, using at least the local memory of the borrower device and the amount of memory borrowed from the lender device; and service accesses by the applications to memory via communication link between the borrower device and the lender device.