公开(公告)号：US11436144B2

公开(公告)日：2022-09-06

申请号：US16846266

申请日：2020-04-10

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski ,  Elliott Clifford Cooper-Balis ,  David Andrew Roberts

IPC: G06F12/0864 ,  G06F12/084 ,  G06F12/0853 ,  G06F12/02 ,  G06F9/30 ,  G06F13/16

Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

公开(公告)号：US11422934B2

公开(公告)日：2022-08-23

申请号：US16937671

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/06

Abstract: Described apparatuses and methods track access metadata pertaining to activity within respective address ranges. The access metadata can be used to inform prefetch operations within the respective address ranges. The prefetch operations may involve deriving access patterns from access metadata covering the respective ranges. Suitable address range sizes for accurate pattern detection, however, can vary significantly from region to region of the address space based on, inter alia, workloads produced by programs utilizing the regions. Advantageously, the described apparatuses and methods can adapt the address ranges covered by the access metadata for improved prefetch performance. A data structure may be used to manage the address ranges in which access metadata are tracked. The address ranges can be adapted to improve prefetch performance through low-overhead operations implemented within the data structure. The data structure can encode hierarchical relationships that ensure the resulting address ranges are distinct.

公开(公告)号：US20220091990A1

公开(公告)日：2022-03-24

申请号：US17543378

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0888 ,  G06F12/0897 ,  G06F12/0862

Abstract: Systems, apparatuses, and methods for memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.

公开(公告)号：US20220019538A1

公开(公告)日：2022-01-20

申请号：US17491119

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for predictive memory access are described. Memory control circuitry instructs a memory array to read a data block from or write the data block to a location targeted by a memory access request, determines memory access information including a data value correlation parameter determined based on data bits used to indicate a raw data value in the data block and/or an inter-demand delay correlation parameter determined based on a demand time of the memory access request, predicts that read access to another location in the memory array will subsequently be demanded by another memory access request based on the data value correlation parameter and/or the inter-demand delay correlation parameter, and instructs the memory array to output another data block stored at the other location to a different memory level that provides faster data access speed before the other memory access request is received.

公开(公告)号：US20210049100A1

公开(公告)日：2021-02-18

申请号：US16538551

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F3/06 ,  G06F9/54

Abstract: Systems, apparatuses, and methods for predictive memory access are described. Memory control circuitry instructs a memory array to read a data block from or write the data block to a location targeted by a memory access request, determines memory access information including a data value correlation parameter determined based on data bits used to indicate a raw data value in the data block and/or an inter-demand delay correlation parameter determined based on a demand time of the memory access request, predicts that read access to another location in the memory array will subsequently be demanded by another memory access request based on the data value correlation parameter and/or the inter-demand delay correlation parameter, and instructs the memory array to output another data block stored at the other location to a different memory level that provides faster data access speed before the other memory access request is received.

公开(公告)号：US20210034539A1

公开(公告)日：2021-02-04

申请号：US16525106

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0888 ,  G06F12/0897 ,  G11C11/22 ,  G06F12/0862

Abstract: Systems, apparatuses, and methods related to memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.

公开(公告)号：US20250156092A1

公开(公告)日：2025-05-15

申请号：US19022888

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Haojie Ye

IPC: G06F3/06

Abstract: Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.

公开(公告)号：US20250004659A1

公开(公告)日：2025-01-02

申请号：US18643936

申请日：2024-04-23

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A controller of a memory system may facilitate data rearrangement within a block-addressable memory device based on metadata associated with prefetching data to a byte-addressable memory device or to a host system. For example, the controller may utilize the metadata and various access commands to rearrange associated data within the block-addressable memory device such that the data is written to a singular superblock of the block-addressable memory device. In some examples, one or more counters may be utilized by the controller to determine whether to rearrange the data within the block-addressable memory device.

公开(公告)号：US20240428853A1

公开(公告)日：2024-12-26

申请号：US18825829

申请日：2024-09-05

Applicant: Micron Technology, Inc.

Inventor： Aliasger Tayeb Zaidy ,  Patrick Alan Estep ,  David Andrew Roberts

IPC: G11C11/54 ,  G06F12/0862 ,  G06F12/0897 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

公开(公告)号：US20240403205A1

公开(公告)日：2024-12-05

申请号：US18615046

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/02

Abstract: Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.