公开(公告)号：US11989088B2

公开(公告)日：2024-05-21

申请号：US17823469

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Emanuele Confalonieri

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/1076

Abstract: Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.

公开(公告)号：US20240126441A1

公开(公告)日：2024-04-18

申请号：US17968049

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Caprí ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

公开(公告)号：US20240070015A1

公开(公告)日：2024-02-29

申请号：US17823469

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0689

Abstract: Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.

公开(公告)号：US20230418755A1

公开(公告)日：2023-12-28

申请号：US18215115

申请日：2023-06-27

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri

IPC: G06F12/0888

CPC classification number: G06F12/0888 ,  G06F2212/60

Abstract: Systems, apparatuses, and methods related to a memory controller for unloaded cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache. The cache can include a cache sequence controller configured to determine a quantity of a pending cache look-up operations, determine the quantity satisfies an unloaded bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

公开(公告)号：US20230229556A1

公开(公告)日：2023-07-20

申请号：US17897048

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Steve Pawlowski ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Paolo Amato

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2211/1009

Abstract: There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.

公开(公告)号：US11687273B2

公开(公告)日：2023-06-27

申请号：US17489336

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Marco Sforzin ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.

公开(公告)号：US20220155997A1

公开(公告)日：2022-05-19

申请号：US16951985

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20220107735A1

公开(公告)日：2022-04-07

申请号：US17552060

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora

IPC: G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G06F11/10

Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.

公开(公告)号：US10916324B2

公开(公告)日：2021-02-09

申请号：US16128113

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10 ,  G11C29/04

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

公开(公告)号：US20200293211A1

公开(公告)日：2020-09-17

申请号：US16890511

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.