公开(公告)号：US20220308796A1

公开(公告)日：2022-09-29

申请号：US17704521

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Massimiliano Patriarca ,  Massimiliano Turconi ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a controller for managing sideband communications are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The controller can provide an additional layer of encryption or decryption for sideband communications between the host and the memory devices connected to the controller. The front end portion receives sideband communications through an interface and is stored by a cache memory within the central controller portion which also comprises an auxiliary security component to encrypt the sideband communications. The back end portion provides a route to the memory devices and the management unit applies the encryption or decryption to the sideband communication.

公开(公告)号：US20220253387A1

公开(公告)日：2022-08-11

申请号：US17169042

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Alessandro Orlando ,  Danilo Caraccio ,  Angelo Alberto Rovelli

IPC: G06F12/1027 ,  G06F3/06 ,  G06F9/455 ,  G06F9/30

Abstract: Systems, apparatuses, and methods related to memory tracing in an emulated computing system are described. Static tracepoints can be inserted into a particular function as part of operating the emulated computing system. By executing the function including the static tracepoints as part of a memory access request, the emulated computing system can receive information corresponding to both a virtual address and a physical address in a real computing system in which data corresponding to the memory access request is stored.

公开(公告)号：US20220207193A1

公开(公告)日：2022-06-30

申请号：US17562916

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/60 ,  G06F21/55 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US20250148133A1

公开(公告)日：2025-05-08

申请号：US19013585

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/10 ,  G06F21/55 ,  G06F21/60 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US20240185938A1

公开(公告)日：2024-06-06

申请号：US18516121

申请日：2023-11-21

Applicant: Micron Technology, Inc.

Inventor： Niccolò Izzo ,  David Hulton ,  Tamara Schmitz ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Danilo Caraccio

IPC: G11C29/08 ,  G11C29/02

CPC classification number: G11C29/08 ,  G11C29/023

Abstract: A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

公开(公告)号：US11803332B2

公开(公告)日：2023-10-31

申请号：US17704521

申请日：2022-03-25

Applicant: Micron Technology, Inc.

Inventor： Massimiliano Patriarca ,  Massimiliano Turconi ,  Angelo Alberto Rovelli

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0632 ,  G06F3/0652 ,  G06F3/0689

Abstract: Systems, apparatuses, and methods related to a controller for managing sideband communications are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The controller can provide an additional layer of encryption or decryption for sideband communications between the host and the memory devices connected to the controller. The front end portion receives sideband communications through an interface and is stored by a cache memory within the central controller portion which also comprises an auxiliary security component to encrypt the sideband communications. The back end portion provides a route to the memory devices and the management unit applies the encryption or decryption to the sideband communication.

公开(公告)号：US12299331B2

公开(公告)日：2025-05-13

申请号：US18583540

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).

公开(公告)号：US20240412805A1

公开(公告)日：2024-12-12

申请号：US18808418

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Craig A. Jones

IPC: G11C29/52 ,  G11C29/02

Abstract: A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

公开(公告)号：US20240184457A1

公开(公告)日：2024-06-06

申请号：US18527990

申请日：2023-12-04

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Federica Cresci

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

Abstract: An access controller can be provided to regulate and secure access to an intermediate memory to which data stored in a one-time-programmable (OTP) memory can be copied. To secure the access of the intermediate memory, the access controller can regulate a frequency at which the intermediate memory can be accessed and cryptographically manage (e.g., encrypt and/or decrypt) data being read from and/or written to the intermediate memory.

公开(公告)号：US11914893B2

公开(公告)日：2024-02-27

申请号：US16951985

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Massimiliano Patriarca ,  Antonino Caprì ,  Emanuele Confalonieri ,  Angelo Alberto Rovelli

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for managed memory systems with multiple priority queues are described. Memory access commands may be received from a host and stored in a command queue. First and second subsets of the commands, respectively associated with first and second priorities, may be determined. The first and second subsets may be routed from the command queue to first and second queues, respectively. The first and second subsets may be processed from the first and second queues to third and fourth queues, respectively, at a storage controller, according to first and second processes that may be run concurrently according to parameters for prioritization between the first and second priorities. Data associated with the commands may be received from the host, temporarily stored in a buffer, then moved to a storage memory (for write commands) or retrieved from the storage memory, temporarily stored in the buffer, then transmitted to the host (for read commands).