公开(公告)号：US20180240511A1

公开(公告)日：2018-08-23

申请号：US15962886

申请日：2018-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Yoshida ,  Hiroki Fujisawa

IPC: G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

Abstract: Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

公开(公告)号：US09570122B2

公开(公告)日：2017-02-14

申请号：US14645124

申请日：2015-03-11

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa

IPC: G11C7/10 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/1048 ,  G11C7/1069 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.

Abstract translation: 一种设备包括第一数据终端，第二数据终端，耦合在数据节点和第一数据终端之间的第一交换缓冲器以及耦合在数据节点和第二数据终端之间的第二交换缓冲器。 第一切换缓冲器和第二切换缓冲器被布置成使得第一切换缓冲器和第二数据终端之间的距离小于第二切换缓冲器和第二数据终端之间的距离，并且第一切换缓冲器和第二切换缓冲器之间的距离 第一数据终端比第二切换缓冲器和第一数据终端之间的距离短。

公开(公告)号：US20150043299A1

公开(公告)日：2015-02-12

申请号：US14341601

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4074 ,  G11C7/1057 ,  G11C7/222 ,  G11C2207/2227

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract translation: 一种设备包括输出电路，DLL（延迟锁定环路）电路，包括接收第一时钟信号的第一延迟线，并且响应于接收到时钟信号而输出提供给输出电路的第二时钟信号，以及ODT 接通ODT激活信号，并且响应于接收到ODT激活信号而输出提供给输出电路的ODT输出信号，以将输出电路设置为电阻终止状态，并且包括第二延迟的ODT电路 线路被配置为由等效延迟量等效于第一延迟线的延迟量由DLL电路设置，ODT输出信号在ODT激活信号处于活动状态的第一时间段期间 通过被设置了等效延迟量的第二延迟线传送而产生。

公开(公告)号：US20150036445A1

公开(公告)日：2015-02-05

申请号：US14447287

申请日：2014-07-30

Applicant: Micron Technology. Inc.

Inventor： Kenji Yoshida ,  Hiroki Fujisawa

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

Abstract translation: 本文公开了一种半导体器件，其包括：存储单元阵列，包括多个存储器组，每个存储器组具有多个存储器单元，所述存储器组由相互不同的地址选择; 第一控制电路响应于第一刷新命令周期性地对存储器组执行刷新操作; 以及第二控制电路，其设定由第一控制电路执行刷新操作的循环。 第二控制电路将周期设置为第一周期，直到在接收到第一刷新命令之后对所有存储器组执行刷新操作，并且第二控制电路将该周期设置为比执行第一刷新命令之后的第一周期长的第二周期 刷新所有内存组的操作。