公开(公告)号：US20200372960A1

公开(公告)日：2020-11-26

申请号：US16989191

申请日：2020-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G06N3/04 ,  G11C16/08 ,  G11C7/10 ,  G11C16/04 ,  G06N3/063

Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.

公开(公告)号：US10529430B2

公开(公告)日：2020-01-07

申请号：US16180154

申请日：2018-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

公开(公告)号：US10482972B2

公开(公告)日：2019-11-19

申请号：US16413708

申请日：2019-05-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26

Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

公开(公告)号：US20190074069A1

公开(公告)日：2019-03-07

申请号：US16180154

申请日：2018-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C16/04 ,  G11C15/00 ,  G11C15/04

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

公开(公告)号：US20190074068A1

公开(公告)日：2019-03-07

申请号：US16180137

申请日：2018-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C16/04 ,  G11C15/00 ,  G11C15/04

Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.

公开(公告)号：US20180225056A1

公开(公告)日：2018-08-09

申请号：US15945316

申请日：2018-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/22

CPC classification number: G06F3/0634 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1064 ,  G06F11/2263 ,  G11C11/005 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

公开(公告)号：US10020058B2

公开(公告)日：2018-07-10

申请号：US15690359

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of memory cells such that pairs of complementary memory cells have complementary states to provide a first minterm, the first minterm comprising a plurality of first variables wherein each variable is enabled responsive to a state of its respective memory cell, and programming a second series string of memory cells of a second group of memory cells such that pairs of complementary memory cells have complementary states to provide a second minterm, the second minterm comprising the first minterm that is enabled responsive to the state of its respective memory cell, the second minterm further comprising a plurality of second variables that are each enabled responsive to the state of their respective memory cell.

公开(公告)号：US09773558B2

公开(公告)日：2017-09-26

申请号：US15132455

申请日：2016-04-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.

公开(公告)号：US20160358661A1

公开(公告)日：2016-12-08

申请号：US15241496

申请日：2016-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G11C7/1006 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/08

Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

Abstract translation: 操作存储器的方法包括产生指示从数据线感测的属性的电平的数据值，同时向连接到该数据线的多个串联连接的存储器单元串的存储器单元的控制栅极施加电位。 操作存储器的方法还包括产生指示从数据线感测的属性的电平的数据值，同时施加电位以控制连接到那些数据线的串联存储器单元的串的存储器单元的栅极，对一组 包括这些数据值的数据值，以及响应于对该组数据值的逻辑运算的输出，确定要应用于串联存储器单元串的不同存储单元的控制栅极的电位。