公开(公告)号：US06625685B1

公开(公告)日：2003-09-23

申请号：US09665989

申请日：2000-09-20

申请人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

发明人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

IPC分类号： G06F1200

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G06F12/0607

摘要： A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations. Furthermore, the portion of the address used to select between interleaved memory sections or interleaved channels may be programmable. One particular implementation may include all of the above programmable features, which may provide a high degree of flexibility in optimizing the memory system.

摘要翻译： 存储器控制器通过一个或多个配置寄存器为存储器的配置提供可编程的灵活性。 可以通过编程配置寄存器来为给定应用优化存储器。 例如，在一个实施例中，用于响应于存储器事务选择用于访问的存储位置的存储器事务的地址部分可以是可编程的。 在为DRAM设计的实现中，可编程地选择第一部分以形成行地址，并且第二部分可以被编程选择以形成列地址。 另外的实施例还可以包括用于选择银行的地址部分的可编程选择。 此外，在一些实现中，分配给不同芯片选择的存储器部分之间的交织模式和在存储器的两个或更多个通道中的交织模式可以是可编程的。 此外，用于在交织的存储器部分或交织的信道之间选择的地址的部分可以是可编程的。 一个具体实现可以包括所有上述可编程特征，其可以在优化存储器系统时提供高度的灵活性。

公开(公告)号：US06560694B1

公开(公告)日：2003-05-06

申请号：US09483755

申请日：2000-01-14

申请人： Kevin J. McGrath ,  James B. Keller

发明人： Kevin J. McGrath ,  James B. Keller

IPC分类号： G06F9355

CPC分类号： G06F9/30189 ,  G06F9/30185 ,  G06F9/342

摘要： A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the operating mode. The operating mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, a first instruction prefix may be coded into an instruction to override the default operand size to a first non-default operand size (e.g. 64 bits). Furthermore, a second instruction prefix may be coded into an instruction in addition to the first instruction prefix to override the default operand size to a second non-default operand size (e.g. 16 bits). Thus operand sizes of 64, 32, and 16 bits may be used when desired.

摘要翻译： 处理器支持默认地址大小大于32位，默认操作数大小为32位的操作模式。 尽管处理器的各种实施例可以在操作模式下实现超过32位，高达并包括64位的任何地址大小，但默认地址大小可以名义上表示为64位。 可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定义状态来建立操作模式。 此外，第一指令前缀可以被编码到用于将默认操作数大小重写为第一非默认操作数大小（例如，64位）的指令。 此外，除了第一指令前缀之外，还可以将第二指令前缀编码为指令，以将默认操作数大小覆盖到第二非默认操作数大小（例如16位）。 因此，当需要时可以使用64位，32位和16位的操作数大小。

公开(公告)号：US06546478B1

公开(公告)日：2003-04-08

申请号：US09418098

申请日：1999-10-14

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F938

CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/384

摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Furthermore, each entry may store additional information regarding the terminating instruction within the entry. In one embodiment, the additional information includes an indication of the branch displacement when the terminating instruction is a branch instruction. In another embodiment, the additional information includes the entry point for a microcode instruction when the terminating instruction is a microcode instruction. Furthermore, the microcode instruction may be identified by an instruction pointer corresponding to a particular decode unit which is coupled to the microcode unit.

摘要翻译： 行预测器缓存对齐信息的指令。 响应于每个提取地址，行预测器提供从取指址开始的指令的对齐信息，以及该指令之后的一个或多个附加指令。 对准信息可以是例如指令指针，每个指令指针直接定位响应于取出地址取出的多个指令字节中的对应指令。 线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 此外，每个条目可以存储关于条目内的终止指令的附加信息。 在一个实施例中，附加信息包括当终止指令是分支指令时分支位移的指示。 在另一个实施例中，当终止指令是微码指令时，附加信息包括微代码指令的入口点。 此外，微代码指令可以由对应于耦合到微代码单元的特定解码单元的指令指针来识别。

公开(公告)号：US06502185B1

公开(公告)日：2002-12-31

申请号：US09476936

申请日：2000-01-03

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3861

摘要： A processor includes an instruction cache and a predecode cache which is not actively maintained coherent with the instruction cache. The processor fetches instruction bytes from the instruction cache and predecode information from the predecode cache. Instructions are provided to a plurality of decode units based on the predecode information, and the decode units decode the instructions and verify that the predecode information corresponds to the instructions. More particularly, each decode unit may verify that a valid instruction was decoded, and that the instruction succeeds a preceding instruction decoded by another decode unit. Additionally, other units involved in the instruction processing pipeline stages prior to decode may verify portions of the predecode information. If the predecode information does not correspond to the fetched instructions, the predecode information may be corrected (either by predecoding the instruction bytes or by updating the predecode information, if the update may be determined without predecoding the instruction bytes). In one particular embodiment, the predecode cache may be a line predictor which stores instruction pointers indexed by a portion of the fetch address. The line predictor may thus experience address aliasing, and predecode information may therefore not correspond to the instruction bytes. However, power may be conserved by not storing and comparing the entire fetch address.

摘要翻译： 处理器包括指令高速缓存和未被主动地保持与指令高速缓存相关联的预解码高速缓存。 处理器从指令高速缓存中获取指令字节，并从预代码高速缓存预先解码信息。 基于预解码信息向多个解码单元提供指令，并且解码单元解码指令并验证预解码信息对应于指令。 更具体地，每个解码单元可以验证有效指令被解码，并且该指令成功接收由另一解码单元解码的先前指令。 此外，涉及在解码之前的指令处理流水线阶段的其他单元可以验证预解码信息的部分。 如果预解码信息不对应于获取的指令，则可以通过预编码指令字节或通过更新预解码信息来校正预解码信息，如果可以在不预编译指令字节的情况下确定更新的话）。 在一个特定实施例中，预解码高速缓存可以是存储由获取地址的一部分索引的指令指针的行预测器。 因此，线预测器可能会遇到地址混叠，因此预解码信息可能不对应于指令字节。 然而，通过不存储和比较整个读取地址可以节省功率。

公开(公告)号：US06385705B1

公开(公告)日：2002-05-07

申请号：US09702147

申请日：2000-10-30

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US06374344B1

公开(公告)日：2002-04-16

申请号：US09200248

申请日：1998-11-25

申请人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

发明人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F1208

CPC分类号： G06F12/0859

摘要： A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.

摘要翻译： 一种技术处理数据处理器内的加载指令，该数据处理器包括具有数据高速缓存的高速缓冲存储器和指示数据高速缓存内的有效条目的标签存储器。 该技术涉及在响应于第一加载指令的四个处理器周期的一系列期间将数据写入数据高速缓存。 此外，该技术涉及在一系列处理器周期中的第一处理器周期期间响应于第一加载指令更新标签存储器并防止标签存储器的读取。 此外，该技术涉及在响应于第二加载指令的第一处理器周期之后的四个处理器周期的系列的处理器周期期间从标签存储器读取标签信息。

公开(公告)号：US06314496B1

公开(公告)日：2001-11-06

申请号：US09099398

申请日：1998-06-18

申请人： Rahul Razdan ,  James B. Keller ,  Richard E. Kessler

发明人： Rahul Razdan ,  James B. Keller ,  Richard E. Kessler

IPC分类号： G06F1200

CPC分类号： G06F12/0815 ,  G06F12/0811

摘要： A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a next coherence state part indicating a next state of the data in the cache. The computing apparatus further includes an execution unit configured to execute the command to change the state of the data stored in the cache according to the next coherence state part of the command.

摘要翻译： 可连接到高速缓存和存储器的计算设备包括被配置为接收原子探测命令的系统端口或具有地址部分的系统数据控制响应命令，该地址部分识别与存储在存储器中的数据相关联的高速缓存中的数据，以及 下一个相干状态部分指示高速缓存中的数据的下一状态。 所述计算装置还包括：执行部，其被配置为根据所述命令的下一个一致状态部分执行改变存储在所述高速缓存中的数据的状态的命令。

公开(公告)号：US5012403A

公开(公告)日：1991-04-30

申请号：US176613

申请日：1988-04-01

申请人： James B. Keller ,  Kevin L. Ladd ,  James J. Reisert

发明人： James B. Keller ,  Kevin L. Ladd ,  James J. Reisert

IPC分类号： G06F9/38

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3863

摘要： An arrangement and method for decoding coded instructions and playing and replaying decoded instructions to a machine. The arrangement has a source of coded instructions. Connected to this coded instruction source is a decoder for receiving and decoding the coded instructions and for outputting the decoded instructions to a machine. A silo is connected to the output of the decoder and siloes and outputs the decoded instructions to the machine. The outputting of the decoded instructions to the machine are switched between the silo and the decoder, so that the machine receives the siloed decoded instructions. By siloing and then replaying already decoded instructions at the time of a trap occurrence, a speed increase is achieved, since the instructions which are in the trap shadow do not have to be decoded again.

摘要翻译： 一种用于解码编码指令并将解码指令播放并重播到机器的装置和方法。 该装置具有编码指令的来源。 连接到该编码指令源的是用于接收和解码编码指令并将解码指令输出到机器的解码器。 筒仓连接到解码器的输出端，并将解码的指令输出到机器。 将解码的指令输出到机器在筒仓和解码器之间切换，使得机器接收经解码的解码指令。 通过在发生陷阱时重新开始并重新播放已解码的指令，由于陷阱阴影中的指令不必再被解码，所以实现了速度增加。

公开(公告)号：US09317285B2

公开(公告)日：2016-04-19

申请号：US13460178

申请日：2012-04-30

申请人： Sandeep Gupta ,  Conrado Blasco-Allue ,  John H. Mylius ,  Gerard R. Williams, III ,  James B. Keller

发明人： Sandeep Gupta ,  Conrado Blasco-Allue ,  John H. Mylius ,  Gerard R. Williams, III ,  James B. Keller

IPC分类号： G06F9/34 ,  G06F9/30 ,  G06F9/38 ,  G06F1/32

CPC分类号： G06F9/30141 ,  G06F1/3234 ,  G06F9/30112 ,  G06F9/384

摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。

公开(公告)号：US20130290680A1

公开(公告)日：2013-10-31

申请号：US13460268

申请日：2012-04-30

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III

IPC分类号： G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3832 ,  G06F9/3857

摘要： A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.

摘要翻译： 一种用于有效减少初始化寄存器的延迟的系统和方法。 处理器内的寄存器重命名单元确定在执行流水线阶段之前是否已知解码的给定指令将目标操作数中的特定数值写入。 一个示例是在其目标操作数中写入值0的移动即时指令。 其他示例也可能符合条件。 如果确定，给定的物理寄存器标识符被分配给目的地操作数，其中给定的物理寄存器标识符与特定数值相关联，但是它不与物理寄存器文件中的实际物理寄存器相关联。 给定的指令被标记为防止它进入执行流水线阶段。 当给定的物理寄存器标识符用于读取物理寄存器文件时，不会访问实际的物理寄存器。