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41.发明授权Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack 有权具有具有多电介质栅叠层的III-V族材料有源区的非平面半导体器件公开(公告)号：US09343574B2
公开(公告)日：2016-05-17
申请号：US14688410
申请日：2015-04-16
IPC分类号： H01L29/00 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/06 , H01L29/205 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/786 , H01L29/201 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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42.发明授权Non-planar semiconductor device having active region with multi-dielectric gate stack 有权具有多电介质栅叠层的有源区的非平面半导体器件公开(公告)号：US09018680B2
公开(公告)日：2015-04-28
申请号：US14340981
申请日：2014-07-25
IPC分类号： H01L29/66 , H01L29/40 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/06 , H01L29/205 , H01L29/423 , H01L29/51 , H01L29/786 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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43.发明授权Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack 有权具有具有多电介质栅叠层的III-V族材料有源区的非平面半导体器件公开(公告)号：US08823059B2
公开(公告)日：2014-09-02
申请号：US13629154
申请日：2012-09-27
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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公开(公告)号：US20140001519A1
公开(公告)日：2014-01-02
申请号：US13538985
申请日：2012-06-29
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/66795 , H01L29/785
摘要： A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.
摘要翻译： 翅片形成在衬底上的第一阻挡层上。 第一阻挡层的带隙大于翅片的带隙。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，并且与沉积在鳍下方的第一阻挡层上的第二势垒层相邻。 在一个实施例中，栅极电介质层沉积在顶表面上，翅片的相对的侧壁和隔离层邻近鳍片下方的第一阻挡层形成。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，隔离层形成在沉积在鳍与第一阻挡层之间的第二势垒层附近。
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公开(公告)号：US09748338B2
公开(公告)日：2017-08-29
申请号：US13538985
申请日：2012-06-29
IPC分类号： H01L29/78 , H01L21/762 , H01L29/10 , H01L29/66
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/66795 , H01L29/785
摘要： A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.
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46.发明申请公开(公告)号：US20140332852A1
公开(公告)日：2014-11-13
申请号：US14340981
申请日：2014-07-25
IPC分类号： H01L29/40 , H01L29/423 , H01L29/205 , H01L29/78 , H01L29/51
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
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47.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20150221762A1
公开(公告)日：2015-08-06
申请号：US14688410
申请日：2015-04-16
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/201 , H01L29/51
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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48.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20160240612A1
公开(公告)日：2016-08-18
申请号：US15135262
申请日：2016-04-21
IPC分类号： H01L29/06 , H01L29/66 , H01L29/423 , H01L29/51 , H01L29/201 , H01L29/205
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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49.发明授权Non-planar semiconductor device having channel region with low band-gap cladding layer 有权具有低带隙包层的沟道区域的非平面半导体器件公开(公告)号：US08785909B2
公开(公告)日：2014-07-22
申请号：US13629148
申请日：2012-09-27
申请人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
发明人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/201 , H01L29/401 , H01L29/42392 , H01L29/66469 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
摘要翻译： 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。
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50.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 有权具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20140084343A1
公开(公告)日：2014-03-27
申请号：US13629154
申请日：2012-09-27
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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