公开(公告)号：US20100052792A1

公开(公告)日：2010-03-04

申请号：US12440977

申请日：2007-09-13

申请人： Koichi Nose ,  Haruya Ishizaki ,  Masayuki Mizuno

发明人： Koichi Nose ,  Haruya Ishizaki ,  Masayuki Mizuno

IPC分类号： H03F3/68

CPC分类号： H03K4/026 ,  H03F1/0294 ,  H03F1/32 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/384 ,  H03K4/92

摘要： [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component.[MEANS FOR SOLVING THE PROBLEMS] The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

摘要翻译： [问题]为了提供例如能够以低电压和低功率工作的脉冲输入型功率放大装置，能有效地抑制谐波分量的产生。 解决问题的手段放大装置包括至少两个放大电路，一个和另外的放大电路，由输出侧相互连接并以相同频率驱动的多个放大器组成。 形成一个放大电路的多个放大器配置有输入和放大参考脉冲的第一反相放大器M12和输入通过移位和反相参考脉冲的相位形成的反相脉冲的第二反相放大器M11。 另一个放大电路配置有第一反相放大器M14和第二反相放大器M13，其中通常输入宽度大于参考脉冲宽度的其它宽脉冲。

公开(公告)号：US07619489B2

公开(公告)日：2009-11-17

申请号：US11687921

申请日：2007-03-19

申请人： Masayuki Mizuno

发明人： Masayuki Mizuno

IPC分类号： H03H7/38

CPC分类号： H01P3/081 ,  H01L23/5225 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.

摘要翻译： 一种包括微带结构的信号传输线的半导体器件，其能够增加信号传输线的特性阻抗并减少多个信号线之间的耦合。 在由信号线和接地板组成的微带结构的信号传输线中，通过在信号线或接地板中形成孔，电线之间的电容降低，并且可以增加特性阻抗。 也可以减少多个信号线之间的耦合。

公开(公告)号：US20090240980A1

公开(公告)日：2009-09-24

申请号：US12441289

申请日：2007-09-13

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F11/20

CPC分类号： G06F11/2043 ,  G06F11/2023 ,  G06F11/2025 ,  G06F11/203 ,  G06F11/2033 ,  G06F11/2035

摘要： An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

摘要翻译： 信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。 信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。 故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元，使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作，切换OS和执行环境， 在故障处理单元上操作，使得它们在替代处理单元上操作，并且切换由故障处理单元使用的共享资源，使得它可用于替代处理单元。

公开(公告)号：US20090189596A1

公开(公告)日：2009-07-30

申请号：US12088411

申请日：2006-09-28

申请人： Koichi Nose ,  Masayuki Mizuno

发明人： Koichi Nose ,  Masayuki Mizuno

IPC分类号： G01R25/00

CPC分类号： G01R19/2509

摘要： An interpolated signal generating circuit (101) generates interpolated signals (SIG1-SIGN) of two consecutive discrete signals (SIG). N measuring circuits (501) measure interpolated signals. Since the interpolated signals are measurement targets, N-times oversampling measurement can also be performed for the discrete signals. With the oversampling measurement, the frequency spectra of the signal components of the discrete signals are maintained, and only the frequency spectrum of a noise component due to a quantization error increases to a high-frequency band, thereby reducing a noise component per unit frequency. Therefore, removing a high-frequency component from a measurement result from each measuring circuit using a low-pass filter (502) makes it possible to improve the signal-to-noise ratio of the measurement result as compared with a case in which no oversampling is performed.

摘要翻译： 内插信号生成电路（101）产生两个连续离散信号（SIG）的内插信号（SIG1-SIGN）。 N个测量电路（501）测量内插信号。 由于内插信号是测量目标，所以也可以对离散信号执行N次过采样测量。 通过过采样测量，维持离散信号的信号分量的频谱，并且只有由于量化误差引起的噪声分量的频谱增加到高频带，从而降低每单位频率的噪声分量。 因此，使用低通滤波器（502）从每个测量电路的测量结果中去除高频分量使得与没有过采样的情况相比，可以提高测量结果的信噪比 被执行。

公开(公告)号：US20090029308A1

公开(公告)日：2009-01-29

申请号：US12280811

申请日：2007-03-15

申请人： Terumasa Ishihara ,  Takaharu Hashimoto ,  Masayuki Mizuno ,  Masaru Morita

发明人： Terumasa Ishihara ,  Takaharu Hashimoto ,  Masayuki Mizuno ,  Masaru Morita

IPC分类号： F27D23/00

CPC分类号： H01L21/324 ,  H01L21/67103

摘要： A heat shield plate for a substrate annealing apparatus is provided with a horizontally supported flat-plate-like substrate 1, a heater 5 positioned above the substrate to heat the upper surface of the substrate with radiation heat, and a heat shield plate 10 horizontally movable between a shielding position where the substrate is shielded from heater and an open position out of the shielding position. The heat shield plate 10 is composed of a structural member 12 made of a low thermal expansion material (carbon composite material) which is hardly deformed due to a temperature difference in the shielding position, and a heat insulating member 14 which covers the upper surface of the structural member and keeps the surface at an allowable temperature or below.

摘要翻译： 用于基板退火装置的隔热板设置有水平支撑的平板状基板1，位于基板上方的加热器5，以用辐射热加热基板的上表面，并且隔热板10水平移动 在基板被屏蔽的屏蔽位置和屏蔽位置之间的打开位置之间。 隔热板10由由遮蔽位置的温度差异而几何变形的低热膨胀性材料（碳复合材料）构成的结构体12，覆盖上述表面的绝热构件14 结构件并将表面保持在允许的温度或更低的温度。

公开(公告)号：US20080175945A1

公开(公告)日：2008-07-24

申请号：US11806035

申请日：2007-05-29

申请人： Masayuki Mizuno ,  Wataru Tomita

发明人： Masayuki Mizuno ,  Wataru Tomita

IPC分类号： B28B7/26

CPC分类号： F16D69/04 ,  F16D2069/0466 ,  F16D2069/0475 ,  F16D2069/0491

摘要： A molding apparatus of a wet friction material has a pair of guide posts vertically extending on a molding apparatus main body. The pair of the guide posts passes through fifteen stages (sixteen pieces) of molding dies. A pair of pantograph-type open-close mechanisms is attached to opposite side surfaces of the molding dies. Thus, the molding dies are piled up on each other so as to come near to each other (mold clamping) and move apart from each other (mold opening). With the pantograph-type open-close link mechanism, all the molding dies are opened and closed at the same time. If the molding dies are slid at a speed of 200 mm/sec, it takes only 3.75 seconds (50 mm*15/200 mm=3.75 sec). It takes a double of that time or 7.5 seconds, that is a half of the time of a related art.

摘要翻译： 湿摩擦材料的成型装置具有在成形装置主体上垂直延伸的一对导柱。 一对导向柱穿过十五个阶段（十六个）成型模具。 一对受电弓型开闭机构连接​​到成型模具的相对侧表面。 因此，成型模具彼此堆叠以彼此靠近（合模）并且彼此分开（模具开口）。 使用缩放式开闭连杆机构，同时打开和关闭所有成型模具。 如果成型模具以200mm / sec的速度滑动，则仅需3.75秒（50mm×15 / 200mm = 3.75秒）。 这需要两倍的时间或7.5秒，这是相关艺术的一半时间。

公开(公告)号：US20070152307A1

公开(公告)日：2007-07-05

申请号：US11687921

申请日：2007-03-19

申请人： Masayuki Mizuno

发明人： Masayuki Mizuno

IPC分类号： H01L39/00

CPC分类号： H01P3/081 ,  H01L23/5225 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.

摘要翻译： 一种包括微带结构的信号传输线的半导体器件，其能够增加信号传输线的特性阻抗并减少多个信号线之间的耦合。 在由信号线和接地板组成的微带结构的信号传输线中，通过在信号线或接地板中形成孔，电线之间的电容降低，并且可以增加特性阻抗。 也可以减少多个信号线之间的耦合。

公开(公告)号：US20050286334A1

公开(公告)日：2005-12-29

申请号：US11151213

申请日：2005-06-14

申请人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Hideaki Saito ,  Yasuhiko Hagihara ,  Muneo Fukaishi ,  Masayuki Mizuno ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： G11C5/04 ,  G11C5/06 ,  G11C8/00 ,  H01L25/065

CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/00

摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

摘要翻译： 具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行 组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片 在堆叠的方向。

公开(公告)号：US06853679B1

公开(公告)日：2005-02-08

申请号：US09653070

申请日：2000-08-31

申请人： Masayuki Mizuno

发明人： Masayuki Mizuno

IPC分类号： G06F3/00 ,  H01L23/522 ,  H03K19/0175 ,  H04B3/36 ,  H04B7/17 ,  H04B17/40 ,  H04L25/20 ,  H04L25/52 ,  H04L29/14 ,  H04B17/02

CPC分类号： H03K19/0175 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect circuit transmits data signals from a first terminal to a second terminal through a data line having a plurality of data driving circuits capable of temporarily interrupting or reestablishing data transmission in a portion of the data line responsive to congestion signals which propagate along a congestion line in a direction opposite the direction of data signal transmission. The congestion signals may be indicative of the status of the second terminal, where a first congestion signal may indicate the second terminal is not receiving data and a second congestion signal may indicate the second terminal is receiving data. Different types of data driving circuits may be cascade-connected in an alternating fashion and may be adapted to interrupt or to reestablish data transmission in sequence starting from the data driving circuit nearest the second terminal of the interconnect and continuing in the direction of the first terminal. The speed with which the first congestion signal and the speed with which the second congestion signal propagate along the congestion line may or may not be equal.

摘要翻译： 互连电路通过具有多个数据驱动电路的数据线将数据信号发送到第二终端，数据线能够响应于沿着拥塞线传播的拥塞信号暂时中断或重新建立数据线的一部分中的数据传输 在与数据信号传输方向相反的方向上。 拥塞信号可以指示第二终端的状态，其中第一拥塞信号可以指示第二终端没有接收数据，并且第二拥塞信号可以指示第二终端正在接收数据。 不同类型的数据驱动电路可以以交替方式级联连接，并且可适于中断或重新建立数据传输，从最靠近互连的第二终端的数据驱动电路开始，并沿第一终端的方向继续 。 第一拥塞信号和第二拥塞信号沿着拥塞线传播的速度的速度可以相同或相等。

公开(公告)号：US06378080B1

公开(公告)日：2002-04-23

申请号：US09472843

申请日：1999-12-28

申请人： Kenichiro Anjo ,  Masayuki Mizuno

发明人： Kenichiro Anjo ,  Masayuki Mizuno

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock distribution circuit is provided with a plurality of blocks each having a plurality of circuits, a first clock driver which distributes a clock signal to each of the blocks, and second clock drivers each provided in one of the blocks. Each second clock drivers distributes the clock signal to each of the circuits in the block. A first wiring is connected between the first clock driver and each of the second clock drivers so that the clock signal arrives at each of the second clock drivers in the same phase. A plurality of second wirings are connected between the second clock drivers and each of the circuits in the block. The second wirings may consist of transmission lines. The second wirings have a maximum length equal to or smaller than a product of clock skew allowable and a propagation velocity of an electromagnetic wave propagating through the second wirings.

摘要翻译： 时钟分配电路具有多个块，每个块具有多个电路，将时钟信号分配给每个块的第一时钟驱动器和分别设置在其中一个块中的第二时钟驱动器。 每个第二个时钟驱动器将时钟信号分配给块中的每个电路。 第一布线连接在第一时钟驱动器和每个第二时钟驱动器之间，使得时钟信号以相同的相位到达每个第二时钟驱动器。 多个第二布线连接在第二时钟驱动器和块中的每个电路之间。 第二条布线可以由传输线组成。 第二配线的最大长度等于或小于允许的时钟偏移乘积和通过第二配线传播的电磁波的传播速度的乘积。