公开(公告)号：US11327884B2

公开(公告)日：2022-05-10

申请号：US16837315

申请日：2020-04-01

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  H04L9/06 ,  H04L9/08 ,  G11C11/56

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US11281392B2

公开(公告)日：2022-03-22

申请号：US16995345

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Aparna U. Limaye ,  Avani F. Trivedi ,  Tomoko Ogura Iwasaki ,  Tracy D. Evans

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/34 ,  G11C16/24 ,  G11C16/04

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.

公开(公告)号：US11238939B2

公开(公告)日：2022-02-01

申请号：US17158555

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US20220019507A1

公开(公告)日：2022-01-20

申请号：US17492220

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Jianmin Huang ,  Xiangang Luo ,  Ashutosh Malshe

IPC: G06F11/20 ,  G06F3/06

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210342191A1

公开(公告)日：2021-11-04

申请号：US17234225

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F9/50 ,  G06F3/06 ,  G06F12/02 ,  G06F9/30

Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

公开(公告)号：US20210303394A1

公开(公告)日：2021-09-30

申请号：US17228425

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Jianmin Huang ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/02

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

公开(公告)号：US11106530B2

公开(公告)日：2021-08-31

申请号：US16723836

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11017847B2

公开(公告)日：2021-05-25

申请号：US16529565

申请日：2019-08-01

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jianmin Huang

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/408 ,  G11C11/4076

Abstract: A processing device in a memory system determines whether a number of a plurality memory commands stored in a queue satisfies a queue depth threshold criterion. Responsive to the queue depth threshold criterion being satisfied, the processing device initiates a high performance mode of operation for the system and executes, in the high performance mode of operation, a first memory command of the plurality of memory commands.

公开(公告)号：US20210151111A1

公开(公告)日：2021-05-20

申请号：US17158555

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10996867B2

公开(公告)日：2021-05-04

申请号：US16506372

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Ting Luo

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027

Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.