公开(公告)号：US20230315332A1

公开(公告)日：2023-10-05

申请号：US17711439

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Olivier Duval ,  Christopher Joseph Bueb

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.

公开(公告)号：US11762798B2

公开(公告)日：2023-09-19

申请号：US16452340

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F13/14 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

CPC classification number: G06F13/4027 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4265 ,  G06F13/4282 ,  G06F2212/657

Abstract: A solid state drive having a drive aggregator configured with multiple host interfaces for parallel and/or redundant connections to one or more host systems. The solid state drive has a plurality of component solid state drives connected to the drive aggregator. Each of the component solid state drives has a controller capable of processing commands from host systems. The drive aggregator is configured to receive commands in the host interfaces concurrently and implement the commands received from the host system using the plurality of component solid state drives.

公开(公告)号：US20230168813A1

公开(公告)日：2023-06-01

申请号：US17456980

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/0754 ,  G06F11/0787

Abstract: Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described. Techniques are described for a memory system to scramble data using different scrambling code parameters when writing the data at different temperatures. Scrambling the data using scrambling code parameters that are based on the temperatures at the time or writing the data may reduce errors introduced into the data by operating the memory cells at extreme temperatures.

公开(公告)号：US11562237B2

公开(公告)日：2023-01-24

申请号：US16840233

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06N3/08 ,  B60W60/00 ,  G06F17/16 ,  G06K9/62 ,  G06N3/063 ,  G06N5/04 ,  G06V10/764 ,  G06N3/04 ,  G06V10/774 ,  G06V10/82

Abstract: Systems, methods and apparatuses of processing overwhelming stimuli in vehicle data recorders. For example, a data recorder can have resources, such as memory components, a controller, an inference engine, etc. The resources can be partitioned into a first subset and a second subset. Abnormal stimuli in an input stream to the recorder may cause delay for real time processing. In response, a time sliced segment of the input stream is selected and assigned to the first subset; and a remaining segment is assigned to the second subset. The first and second subsets can separately process the time sliced segment and the remaining segment in parallel and thus avoid delay in the processing of the remaining segment. An artificial neural network (ANN) can determine a width for selecting the segment processed by the first subset; and the processing result can include a preferred width used to train the ANN.

公开(公告)号：US20220200630A1

公开(公告)日：2022-06-23

申请号：US17694280

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: H03M13/29 ,  H03M13/35 ,  G06F11/10

Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

公开(公告)号：US11055249B2

公开(公告)日：2021-07-06

申请号：US16452366

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F13/40 ,  G06F13/16

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

公开(公告)号：US20210173803A1

公开(公告)日：2021-06-10

申请号：US17180623

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F13/40 ,  G06F12/10 ,  G06F13/16 ,  G06F13/42

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

公开(公告)号：US10942846B2

公开(公告)日：2021-03-09

申请号：US16452369

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F13/38 ,  G06F12/10 ,  G06F13/40

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.