公开(公告)号：US20190108108A1

公开(公告)日：2019-04-11

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20190035461A1

公开(公告)日：2019-01-31

申请号：US16124222

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US20180129575A1

公开(公告)日：2018-05-10

申请号：US15345862

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/2094 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.