公开(公告)号：US11735234B2

公开(公告)日：2023-08-22

申请号：US17557825

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C27/02 ,  G11C7/06 ,  H03F3/45 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C7/062 ,  G11C11/15 ,  G11C11/1657 ,  H03F3/45076

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

公开(公告)号：US11688448B2

公开(公告)日：2023-06-27

申请号：US17470573

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273

Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.

公开(公告)号：US11545206B2

公开(公告)日：2023-01-03

申请号：US17236741

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

Abstract: Methods, systems, and devices for differential amplifier schemes for non-switching state compensation are described. During a read operation, a first node of a memory cell may be coupled with an input of differential amplifier while a second node of the memory cell may be biased with a first voltage (e.g., to apply a first read voltage across the memory cell). The second node of the memory cell may subsequently be biased with a second voltage (e.g., to apply a second read voltage across the memory cell), which may support the differential amplifier operating in a manner that compensates for a non-switching state of the memory cell. By compensating for a non-switching state of a memory cell during read operations, read margins may be increased.

公开(公告)号：US11322196B2

公开(公告)日：2022-05-03

申请号：US17078806

申请日：2020-10-23

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/08 ,  G11C11/22 ,  G11C16/26 ,  G11C16/08

Abstract: Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.

公开(公告)号：US20220076724A1

公开(公告)日：2022-03-10

申请号：US17470573

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.

公开(公告)号：US20210201976A1

公开(公告)日：2021-07-01

申请号：US17143728

申请日：2021-01-07

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.

公开(公告)号：US10943633B2

公开(公告)日：2021-03-09

申请号：US16583033

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22 ,  G11C29/00 ,  G11C11/56

Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

公开(公告)号：US20210020222A1

公开(公告)日：2021-01-21

申请号：US16514481

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.

公开(公告)号：US10896714B1

公开(公告)日：2021-01-19

申请号：US16514481

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.

公开(公告)号：US20200279590A1

公开(公告)日：2020-09-03

申请号：US16877133

申请日：2020-05-18

Applicant: Micron Technology, Inc

Inventor： Mahdi Jamali ,  William A. Melton ,  Daniele Vimercati ,  Xinwei Guo ,  Yasuko Hattori

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/22

Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.