公开(公告)号：US06829175B2

公开(公告)日：2004-12-07

申请号：US10289866

申请日：2002-11-06

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu ,  Samuel C. Pan

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu ,  Samuel C. Pan

IPC分类号： G11C700

CPC分类号： G11C16/14

摘要： An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

摘要翻译： 提供了一种用于非易失性存储器的存储单元的擦除方法。 每个存储单元包括栅极，源极，漏极，电子俘获层和衬底。 通过向控制栅极施加第一电压，向源施加第二电压，向漏极施加第三电压并向衬底施加第四电压来擦除存储单元内的数据。 通过负栅极F-N隧道效应将电子从电子捕获层拉入沟道。

公开(公告)号：US06690601B2

公开(公告)日：2004-02-10

申请号：US10113356

申请日：2002-03-29

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1600

CPC分类号： G11C16/0475 ,  H01L21/28273 ,  H01L29/792 ,  H01L29/7923

摘要： A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a P type semiconductor substrate with a N+ source and a N+ drain being formed on the semiconductor substrate, a channel being formed between the source and the drain. A first isolating layer, a nonconducting charge trapping layer, a second isolating layer and a gate are sequentially formed above the channel. The trapping layer stores an amount of electrons as the nonvolatile memory cell is erased.

摘要翻译： 本发明的优选实施例提供一种捕获非易失性存储单元，其包括在半导体衬底上形成有N +源极和N +漏极的P型半导体衬底，在源极和漏极之间形成沟道。 在通道上方依次形成第一隔离层，不导电电荷俘获层，第二隔离层和栅极。 当非易失性存储单元被擦除时，捕获层存储一定量的电子。

公开(公告)号：US07875938B2

公开(公告)日：2011-01-25

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/51

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20090108345A1

公开(公告)日：2009-04-30

申请号：US12325824

申请日：2008-12-01

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/78

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US07348625B2

公开(公告)日：2008-03-25

申请号：US11194545

申请日：2005-08-02

申请人： Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/788

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

摘要翻译： EEPROM单元在电荷保持绝缘层的相对侧上包括第一和第二辅助栅极。 在EEPROM存储器单元中的电流在反应层之间流动，反应层响应于施加到辅助栅极的偏置而产生。 绝缘层可以包括氮化硅，其设置在沟道区域上方的二氧化硅层之间，使得这些层可以构成电介质叠层，其可被制造成占据相对小的面积。

公开(公告)号：US07473625B2

公开(公告)日：2009-01-06

申请号：US11100688

申请日：2005-04-07

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L21/3205

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.

摘要翻译： 提供LDMOS器件和制造方法。 LDMOS器件具有在衬底中形成有源区和漏区的衬底。 在源极和漏极区域之间的衬底的一部分上设置绝缘层，使得在绝缘层和衬底的表面之间提供平面界面。 然后在绝缘层的一部分上形成绝缘构件，并且在绝缘构件和绝缘层的一部分上形成栅极层。 通过采用这种结构，已经发现存在能够在保持高击穿电压的同时降低导通电阻的平坦电流路径。

公开(公告)号：US20070158741A1

公开(公告)日：2007-07-12

申请号：US11684830

申请日：2007-03-12

申请人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

发明人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78627

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

摘要翻译： 提供横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 该方法包括以下步骤：（a）提供第一导电类型的衬底; （b）在所述衬底内形成第二导电类型的阱区，所述阱区具有超陡逆向（SSR）阱分布，其中掺杂浓度随着深度而变化，以便在表面区域中提供较轻的掺杂浓度 所述阱区域比在所述阱区域的所述表面区域以下的区域中的区域大; （c）形成部分覆盖所述阱区并与所述阱区绝缘的栅极层; 以及（d）在所述阱区域中形成源极区域和漏极区域中的一个。 SSR阱区域的存在提供了更轻的表面掺杂，以使得能够在LDMOS器件内获得更高的击穿电压，并且进行较重的次表面掺杂以降低导通电阻。

公开(公告)号：US20060189081A1

公开(公告)日：2006-08-24

申请号：US11063932

申请日：2005-02-23

申请人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

发明人： Chia-Lun Hsu ,  Mu-Yi Liu ,  Tao-Cheng Lu ,  Ichen Yang ,  Kuan-Po Chen

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78627

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

摘要翻译： 提供横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 该方法包括以下步骤：（a）提供第一导电类型的衬底; （b）在所述衬底内形成第二导电类型的阱区，所述阱区具有超陡逆向（SSR）阱分布，其中掺杂浓度随着深度而变化，以便在表面区域中提供较轻的掺杂浓度 所述阱区域比在所述阱区域的所述表面区域以下的区域中的区域大; （c）形成部分覆盖所述阱区并与所述阱区绝缘的栅极层; 以及（d）在所述阱区域中形成源极区域和漏极区域中的一个。 SSR阱区域的存在提供了更轻的表面掺杂，以使得能够在LDMOS器件内获得更高的击穿电压，并且进行较重的次表面掺杂以降低导通电阻。

公开(公告)号：US20060033149A1

公开(公告)日：2006-02-16

申请号：US11194545

申请日：2005-08-02

申请人： Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/788

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

摘要翻译： EEPROM单元在电荷保持绝缘层的相对侧上包括第一和第二辅助栅极。 在EEPROM存储器单元中的电流在反应层之间流动，反应层响应于施加到辅助栅极的偏置而产生。 绝缘层可以包括氮化硅，其设置在沟道区域上方的二氧化硅层之间，使得这些层可以构成电介质叠层，其可被制造成占据相对小的面积。

公开(公告)号：US20060017102A1

公开(公告)日：2006-01-26

申请号：US11100688

申请日：2005-04-07

申请人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chia-Lun Hsu ,  Ichen Yang ,  Kuan-Po Chen ,  Tao-Cheng Lu

IPC分类号： H01L29/76 ,  H01L21/8232

CPC分类号： H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S438/981

摘要： An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.