摘要:
A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.
摘要:
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Bus transactions to a selected slave are monitored to determine possible conflicts when multiple masters may be addressing the slave. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, by a selected address range or alternatively by external trigger events.
摘要:
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.
摘要:
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.
摘要:
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information from the caches is associated with a common address. The processor also provides the information to a user of the software.
摘要:
Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace program that, when executed by a processor, causes the processor to display trace data on a display device (the trace data comprising a plurality of addresses of instructions executed by a target processor), enable a user of the debug-trace program to select an address of the plurality of addresses to create a selected address, and display data based on an operating context proximate in time to when the instruction of the selected address was executed on the target processor.
摘要:
A method and system of profiling applications that use virtual memory. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of tasks, each task using a different virtual to physical memory mapping), obtaining values indicative of a plurality of states of virtual to physical memory mapping used by a memory management unit associated with a processor of a target system, and displaying an indication of a proportion of an execution time the processor of the target system dedicated to each of a plurality of tasks during the execution time.
摘要:
A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of overlays of the traced program has executed on the target system, and displaying on a display device an indication of a proportion of an execution time on the processor of the target system dedicated to each of the plurality of overlay programs.
摘要:
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels. The caches comprise a plurality of cache line addresses, each cache line address associated with a corresponding name. The software causes the processor to display the information on a graphical user interface (GUI), the GUI cross-referencing each of the cache line addresses with a corresponding name.
摘要:
An orienting apparatus including at least one housing element configured to couple with a drill string; an actuator disposed inside the at least one housing element; a nozzle coupled to the actuator; a torque generator coupled to the actuator and extending axially downward through the at least one housing, wherein the torque generator is configured to rotate in a first direction as it moves downward; a mandrel coupled to the torque generator; and a stroke adjuster at least partially disposed in an upper end of the mandrel, wherein rotation in the first direction is caused by an increase in differential pressure is disclosed.