公开(公告)号：US20220200166A1

公开(公告)日：2022-06-23

申请号：US17129084

申请日：2020-12-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Jeahyeong HAN ,  Mohammad Ali TASSOUDJI

IPC: H01Q21/06 ,  H01Q1/48 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q21/00

Abstract: Aspects disclosed herein include a device including a first antenna substrate including one or more antennas. The device also includes a metallization structure. The device also includes a first spacer disposed between the first antenna substrate and the metallization structure, configured to maintain a constant distance between the first antenna substrate and the metallization structure. The device also includes a first plurality of conductive elements, disposed within the first spacer, configured to electrically couple the first antenna substrate to the metallization structure. The device also includes where the first spacer is configured to enclose all the conductive elements, electrically coupled to the first antenna substrate, and is configured to form an air gap between the first antenna substrate and the metallization structure. The device also includes where the first plurality of conductive elements is separated by air in the air gap.

公开(公告)号：US20210375712A1

公开(公告)日：2021-12-02

申请号：US16883812

申请日：2020-05-26

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Jonghae KIM

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/3065 ,  H01L23/373

Abstract: A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

公开(公告)号：US20210313266A1

公开(公告)日：2021-10-07

申请号：US16840752

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.

公开(公告)号：US20210272931A1

公开(公告)日：2021-09-02

申请号：US16803804

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Zhijie WANG ,  Hong Bok WE

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A package comprising a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure and the substrate are coupled together in such a way that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels through at least the substrate, then through the interconnect structure and back through the substrate.

公开(公告)号：US20210249359A1

公开(公告)日：2021-08-12

申请号：US16783768

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Bohan YAN ,  Hong Bok WE

IPC: H01L23/552 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L21/50

Abstract: Examples herein include better heat transfer from application processor(s) and power management system without affecting the EMI performance. In one example, a thermal solution structure improves thermal performance of a modular system with better EMI shielding with the addition of heat conduction pillars from the substrate metal layer to TIM material, which thereafter connects to a heat pipe. The pillar transfers heat from substrate to heat pipe and connects physically to a global ground reference net of the IC package and eventually to a system motherboard while the pillar shields components inside the array/ring. This gives both a thermal and EMI shield solution in a single structure.

公开(公告)号：US20210066197A1

公开(公告)日：2021-03-04

申请号：US16553283

申请日：2019-08-28

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Jaehyun YEON

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/50 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.

公开(公告)号：US20200219803A1

公开(公告)日：2020-07-09

申请号：US16724247

申请日：2019-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Chin-Kwan KIM ,  Aniket PATIL ,  Jaehyun YEON

IPC: H01L23/498 ,  H01L21/48

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US20250125244A1

公开(公告)日：2025-04-17

申请号：US18605481

申请日：2024-03-14

Applicant: QUALCOMM Incorporated

Inventor： Manuel ALDRETE ,  Rajneesh KUMAR ,  Zhijie WANG ,  Aniket PATIL ,  Srikanth KULKARNI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the interposer structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the base structure. A width of the bond ball portion is greater than a width of the bond wire portion.

公开(公告)号：US20250096094A1

公开(公告)日：2025-03-20

申请号：US18468474

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Piyush GUPTA ,  Durodami LISK

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18

Abstract: Disclosed are package devices that include interconnects on first and second surfaces of a package substrate. The interconnects on the first surface of the package substrate are configured to carry general purpose input-output (GPIO) and miscellaneous IO signals. The interconnects on the second surface of the package substrate are configured to carry high speed input-output (HSIO) signals-signals whose speeds are above some minimum speed threshold. In this way, the package form can be reduced while still allowing for increased number of IO signals to be delivered.

公开(公告)号：US20250079277A1

公开(公告)日：2025-03-06

申请号：US18457162

申请日：2023-08-28

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Manuel ALDRETE ,  Zhijie WANG ,  Piyush GUPTA ,  Rajneesh KUMAR

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

Abstract: An integrated circuit (IC) device includes a substrate. The substrate includes a first side having a stepped configuration having a first surface that is elevated relative to a second surface. The first surface includes first solder resist openings (SROs), and the second surface includes second SROs. The IC device includes a first set of solder balls electrically connected to a first set of contacts in the first SROs. A solder ball of the first set of solder balls has a first characteristic dimension. The IC device also includes a second set of solder balls electrically connected to a second set of contacts in the second SROs. A solder ball of the second set of solder balls has a second characteristic dimension larger than the first characteristic dimension.