公开(公告)号：US20210143152A1

公开(公告)日：2021-05-13

申请号：US16678320

申请日：2019-11-08

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a gate-cut isolation structure. An example method of fabricating semiconductor device generally includes forming a dielectric region between a first semiconductor region and a second semiconductor region. The method also includes forming a first gate region disposed above and spanning a width of the dielectric region between the first and second semiconductor regions, wherein the first gate region is also disposed above at least a portion of the first semiconductor region and above at least a portion of the second semiconductor region. The method further includes concurrently forming an SDB and a gate-cut isolation structure, wherein the SDB intersects the first and second semiconductor regions and wherein the gate-cut isolation structure electrically separates the first gate region into a first portion associated with the first semiconductor region and a second portion associated with the second semiconductor region.

公开(公告)号：US20210028115A1

公开(公告)日：2021-01-28

申请号：US16517845

申请日：2019-07-22

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Haining YANG ,  Jun YUAN

IPC: H01L23/532 ,  H01L23/535 ,  H01L29/45 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to an integrated device including a low parasitic middle-of-line (MOL) structure. The integrated device generally includes a plurality of semiconductor devices; an MOL structure disposed above the plurality of semiconductor devices and comprising a dielectric layer; a first barrier-less conductor extending between a first terminal of a semiconductor device in the plurality of semiconductor devices and into the MOL structure; and a first air gap disposed between a lateral surface of an upper portion of the first barrier-less conductor and the dielectric layer of the MOL structure.

公开(公告)号：US20200176330A1

公开(公告)日：2020-06-04

申请号：US16204949

申请日：2018-11-29

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: Aspects of the disclosure are directed to isolation in integrated circuits. In accordance with one aspect, implementing a complementary metal oxide semiconductor (CMOS) isolation in an integrated circuit (IC) includes etching an interlayer dielectric (ILD) between two of a plurality of gates in a first section of an integrated circuit (IC); etching a semiconductor substrate to form a trench within an active region in the first section; and filling the trench with an insulator in the first section and planarizing the integrated circuit (IC).

公开(公告)号：US20200044440A1

公开(公告)日：2020-02-06

申请号：US16362417

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Xiangdong CHEN ,  Haining YANG ,  Kern RIM

IPC: H02H9/04 ,  H01Q1/22 ,  H02J7/00

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

公开(公告)号：US20180219009A1

公开(公告)日：2018-08-02

申请号：US15418651

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

公开(公告)号：US20160300948A1

公开(公告)日：2016-10-13

申请号：US14680711

申请日：2015-04-07

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Yanxiang LIU

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract translation: 半导体鳍片包括沟道区域。 由金属形成的闸应力部件横向于翅片延伸并且包括在通道区域中跨过翅片的门表面。 闸门应力器构件具有包括与翅片间隔开切割距离的部分切割的构造。 该结构通过栅极表面导致鳍中的横向应力，其具有对应于切割距离的大小。 由金属形成的横向应力器构件在通道区域外的区域跨越翅片，并且在通道区域外的区域处引起翅片中额外的横向应力。 对应于切割距离的大小与附加的横向应力相结合，在通道区域中引起纵向压缩应变。