公开(公告)号：US20250096139A1

公开(公告)日：2025-03-20

申请号：US18468366

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed are devices that may incorporate airgaps in top signal layers and/or power layers on a frontside of a substrate. Alternatively, or in addition thereto, airgaps may also be incorporated in signal layers and/or power layers on a backside of the substrate. In this way, metal capacitances of the devices may be reduced, which thereby improves performance of semiconductor circuits such as CPUs.

公开(公告)号：US20210343830A1

公开(公告)日：2021-11-04

申请号：US16866316

申请日：2020-05-04

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Ye LU ,  Junjing BAO

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.

公开(公告)号：US20210320059A1

公开(公告)日：2021-10-14

申请号：US16846591

申请日：2020-04-13

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  John Jianhong ZHU ,  Lixin GE

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528

Abstract: Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

公开(公告)号：US20220336346A1

公开(公告)日：2022-10-20

申请号：US17234166

申请日：2021-04-19

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Haining YANG

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/552

Abstract: A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

公开(公告)号：US20210320175A1

公开(公告)日：2021-10-14

申请号：US16844699

申请日：2020-04-09

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  John Jianhong ZHU

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain.

公开(公告)号：US20210217699A1

公开(公告)日：2021-07-15

申请号：US16738127

申请日：2020-01-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail comprises a first conductive layer, a barrier layer, and a second conductive layer comprising copper. The barrier layer is disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20150249038A1

公开(公告)日：2015-09-03

申请号：US14274099

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  John Jianhong ZHU ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract translation: 半导体器件包括具有将第一互连层耦合到沟槽的通孔的管芯。 半导体器件还包括在沟槽的侧壁和相邻表面上以及在通孔的侧壁上的阻挡层。 半导体器件在第一互连层的表面上具有掺杂的导电层。 掺杂导电层在通孔的侧壁之间延伸。 半导体器件还包括在通孔和沟槽中的阻挡层上的导电材料。 导电材料位于设置在第一互连层表面上的掺杂导电层上。

公开(公告)号：US20250046716A1

公开(公告)日：2025-02-06

申请号：US18365791

申请日：2023-08-04

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A via with a modified reverse selective barrier structure and method for making the same are disclosed. In an aspect, a via structure comprises a first metal structure providing an electrical conductor (e.g., copper) oriented vertically; a second structure (e.g., cobalt) surrounding and in contact with a bottom and sides of the first metal structure; a third structure (e.g., metallic tantalum) surrounding and in contact with a bottom and sides of the second structure; a fourth structure (e.g., ruthenium) disposed beneath and in contact with a bottom of the third structure; and a fifth structure (e.g., amorphous tantalum nitride) surrounding and in contact with sides of the third structure; wherein a bottom surface of the fourth structure is in contact with a top surface of a metallization layer. In some aspects, the fifth structure is also surrounding and in contact with sides of the fourth structure.

公开(公告)号：US20210005604A1

公开(公告)日：2021-01-07

申请号：US16918770

申请日：2020-07-01

Applicant: Qualcomm Incorporated

Inventor： Lixin GE ,  Ye LU ,  John Jianhong ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/66

Abstract: Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel and a first set of work function layer. The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel and a second set of work function layer. The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。