公开(公告)号：US20180122824A1

公开(公告)日：2018-05-03

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20160351490A1

公开(公告)日：2016-12-01

申请号：US14723357

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON

IPC: H01L23/528 ,  H01L27/088

CPC classification number: H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract translation: MOS器件包括第一，第二，第三和第四互连。 第一互连在第一方向上在第一轨道上延伸。 第一互连配置在金属层中。 第二互连在第一方向上在第一轨道上延伸。 第二互连配置在金属层中。 第三互连在第一方向上的第二轨道上延伸。 第三互连配置在金属层中。 第二条轨道平行于第一条轨道。 第三互连耦合到第二互连。 第二和第三互连被配置为提供第一信号。 第四互连在第一方向上在第二轨道上延伸。 第四互连配置在金属层中。 第四互连耦合到第一互连。 第一和第四互连配置成提供与第一信号不同的第二信号。

公开(公告)号：US20200266821A1

公开(公告)日：2020-08-20

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20190252408A1

公开(公告)日：2019-08-15

申请号：US15895094

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Xiangdong CHEN ,  Renukprasad HIREMATH ,  Rui LI ,  Venugopal BOYNAPALLI

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11816 ,  H01L2027/11855 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

公开(公告)号：US20190173473A1

公开(公告)日：2019-06-06

申请号：US16267289

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20200176562A1

公开(公告)日：2020-06-04

申请号：US16781820

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532

Abstract: In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

公开(公告)号：US20170365657A1

公开(公告)日：2017-12-21

申请号：US15186326

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Satyanarayana SAHU ,  Venugopal BOYNAPALLI

IPC: H01L29/06 ,  H01L27/02 ,  H01L23/535

CPC classification number: H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

公开(公告)号：US20160343661A1

公开(公告)日：2016-11-24

申请号：US15159744

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Stanley Seungchul SONG ,  Kern RIM ,  John Jianhong ZHU

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L27/0207

Abstract: A MOS device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The MOS device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer. The MOS device further includes a gate interconnect extending in a second direction orthogonal to the first direction, the gate interconnect being situated in a first layer below the metal layer, wherein the gate interconnect is coupled to the first interconnect by a first via. The MOS device further includes a third interconnect extending in the second direction, the third interconnect being coupled to both the first and second interconnects, wherein the third interconnect is coupled to the first interconnect by a second via, and wherein the second via contacts the first via.

Abstract translation: MOS器件包括沿第一方向延伸的第一互连，第一互连配置在金属层中。 MOS器件还包括在第一方向上平行于第一互连延伸的第二互连，第二互连配置在金属层中。 MOS器件还包括在与第一方向正交的第二方向上延伸的栅极互连，栅极互连位于金属层下方的第一层中，其中栅极互连通过第一通孔耦合到第一互连。 MOS器件还包括在第二方向上延伸的第三互连，第三互连件耦合到第一和第二互连件，其中第三互连通过第二通孔耦合到第一互连，并且其中第二通孔接触第一互连 通过。

公开(公告)号：US20150302129A1

公开(公告)日：2015-10-22

申请号：US14255677

申请日：2014-04-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Mukul GUPTA ,  Ohsang KWON ,  Foua VANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/70466

Abstract: In an embodiment, a method in the manufacture of triple-patterning lithography masks, each mask represented by one of three colors, where each cell layout has exactly one polygonal pattern at one-half the different-color spacing from its left boundary, and exactly one polygonal pattern at one-half the different-color spacing from its right boundary. During placement of the cell layouts into a row, the method includes switching assigned colors in a cell layout to ensure that no two polygonal patterns of the same color in the layout are at a distance from each other less than the same-color spacing.

Abstract translation: 在一个实施例中，制造三重图案化光刻掩模的方法，每个掩模由三种颜色之一表示，其中每个单元布局具有与其左边界不同的颜色间隔的一半的正好一个多边形图案，并且精确地 一个多边形图案与其右边界的不同颜色间距的一半。 在将单元格布局放置到行中的过程中，该方法包括切换单元格布局中分配的颜色，以确保布局中相同颜色的两个多边形图案彼此之间的距离小于相同颜色的间距。

公开(公告)号：US20150221639A1

公开(公告)日：2015-08-06

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Satyanarayana SAHU ,  Divya GANGADHARAN ,  Chih-lung KAO ,  Renukprasad Shreedhar HIREMATH ,  Animesh DATTA ,  Qi YE

IPC: H01L27/088 ,  G06F17/50 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压，并且在栅极的另一侧上的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。