公开(公告)号：US20220123101A1

公开(公告)日：2022-04-21

申请号：US17074026

申请日：2020-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jun YUAN ,  Haining YANG ,  Bin YANG

IPC: H01L49/02 ,  H01L23/522

Abstract: Disclosed are examples of 3D metal-insulator-metal (MIM) capacitor structures, e.g., in semiconductor packages. The disclosed 3D MIM capacitors provide high capacitance in small areas. As such, the disclosed 3D MIM capacitors may be used as decoupling capacities for high performance computing (HPC) processors.

公开(公告)号：US20240105728A1

公开(公告)日：2024-03-28

申请号：US18472074

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Jun YUAN ,  Giridhar NALLAPATI ,  Deepak SHARMA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

公开(公告)号：US20210118883A1

公开(公告)日：2021-04-22

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Stanley Seungchul SONG ,  Jun YUAN ,  Kern RIM

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

公开(公告)号：US20180197743A1

公开(公告)日：2018-07-12

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28123 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20220285491A1

公开(公告)日：2022-09-08

申请号：US17189755

申请日：2021-03-02

Applicant: QUALCOMM Incorporated

Inventor： Ming-Huei LIN ,  Lunwei CHANG ,  Jun YUAN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A transistor cell height may be scaled down without producing undesirable degradation with the use of an isolation structure between adjacent fins of a transistor cell. The transistor cell includes a substrate, a first fin and a second fin located on the substrate, and an isolation structure located on the substrate between the first fin and the second fin.

公开(公告)号：US20220109053A1

公开(公告)日：2022-04-07

申请号：US17061709

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun YUAN ,  Peijie FENG

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

公开(公告)号：US20210028115A1

公开(公告)日：2021-01-28

申请号：US16517845

申请日：2019-07-22

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Peijie FENG ,  Haining YANG ,  Jun YUAN

IPC: H01L23/532 ,  H01L23/535 ,  H01L29/45 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to an integrated device including a low parasitic middle-of-line (MOL) structure. The integrated device generally includes a plurality of semiconductor devices; an MOL structure disposed above the plurality of semiconductor devices and comprising a dielectric layer; a first barrier-less conductor extending between a first terminal of a semiconductor device in the plurality of semiconductor devices and into the MOL structure; and a first air gap disposed between a lateral surface of an upper portion of the first barrier-less conductor and the dielectric layer of the MOL structure.

公开(公告)号：US20180082846A1

公开(公告)日：2018-03-22

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.