公开(公告)号：US20230142048A1

公开(公告)日：2023-05-11

申请号：US17986781

申请日：2022-11-14

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G11C7/1072 ,  G06F2212/283 ,  G06F2212/656

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US10853261B2

公开(公告)日：2020-12-01

申请号：US16157908

申请日：2018-10-11

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US20190317907A1

公开(公告)日：2019-10-17

申请号：US16365528

申请日：2019-03-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C11/4076 ,  G06F9/48 ,  G06F13/40 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20190198081A1

公开(公告)日：2019-06-27

申请号：US16211956

申请日：2018-12-06

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali ,  Frederick A. Ware

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G06F12/08 ,  G06F12/1009 ,  Y02D10/13

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

公开(公告)号：US10157657B2

公开(公告)日：2018-12-18

申请号：US13975873

申请日：2013-08-26

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  James Tringali ,  Frederick A. Ware

IPC: G11C11/00 ,  G11C11/406 ,  G06F12/08 ,  G06F12/1009

Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.

公开(公告)号：US20170242807A1

公开(公告)日：2017-08-24

申请号：US15428121

申请日：2017-02-08

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/16 ,  G06F9/48 ,  G06F13/40 ,  G11C11/4094 ,  G11C11/4076

CPC classification number: G06F13/1673 ,  G06F9/4881 ,  G06F13/1678 ,  G06F13/4059 ,  G06F2209/486 ,  G06F2209/5018 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US20140164823A1

公开(公告)日：2014-06-12

申请号：US14098322

申请日：2013-12-05

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness ,  Mehmet Günhan Ertosun ,  Ian P. Shaeffer

IPC: G06F11/20

CPC classification number: G06F11/2053 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431 ,  G11C29/50008 ,  G11C29/52 ,  G11C2029/0409

Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

Abstract translation: 诸如存储器控制器和存储器件的存储器系统的组件，其在累积的存储器读出干扰之前检测累积的存储器读取干扰并且在达到导致错误的电平之前校正这种干扰。 存储器件包括存储器阵列和干扰控制电路。 存储器阵列包括多个存储器行。 每个存储器行与具有对应于存储器行中的累积干扰的状态的干扰警告电路相关联。 干扰控制电路响应于由行访问命令指定的多个存储行的存储器行的激活，基于与存储器相关联的干扰警告电路的状态来确定存储器行中是否存在干扰条件 行。 如果存在干扰条件，则扰动控制电路使得对存储器行进行恢复操作以减少累积的干扰。