公开(公告)号：US20180336089A1

公开(公告)日：2018-11-22

申请号：US15963163

申请日：2018-04-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US09098209B2

公开(公告)日：2015-08-04

申请号：US14064167

申请日：2013-10-27

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序地写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

公开(公告)号：US08938578B2

公开(公告)日：2015-01-20

申请号：US13936777

申请日：2013-07-08

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Renu Rangnekar

IPC: G06F12/00 ,  G11C11/4063 ,  G11C7/10

CPC classification number: G11C11/4063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal.

Abstract translation: 公开了一种集成电路存储器件。 存储器件包括具有用于接收时钟信号的定时输入的存储器芯。 接口耦合到内存核心。 该接口包括用于接收写入数据位的串行流的接收器和由选通信号计时的采样器，以产生串行化写入数据。 该接口还包括解串器和控制逻辑。 解串器包括用于接收串行写入数据的输入端和响应于由控制逻辑产生的控制信号产生并行数据的输出端。 在第一操作模式中，控制逻辑产生相对于时钟信号的控制信号。 在第二操作模式中，控制逻辑产生关于选通信号的控制信号。

公开(公告)号：US20140082234A1

公开(公告)日：2014-03-20

申请号：US14064167

申请日：2013-10-27

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

公开(公告)号：US12230355B2

公开(公告)日：2025-02-18

申请号：US17634370

申请日：2020-08-13

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Liji Gopalakrishnan ,  Thomas Vogelsang

IPC: G11C7/10 ,  G11C7/22

Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

公开(公告)号：US12050513B2

公开(公告)日：2024-07-30

申请号：US18306542

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John E. Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US20230281137A1

公开(公告)日：2023-09-07

申请号：US18117119

申请日：2023-03-03

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G06F13/1668 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

公开(公告)号：US11675657B2

公开(公告)日：2023-06-13

申请号：US17721735

申请日：2022-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John E. Linstadt ,  Liji Gopalakrishnan

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

公开(公告)号：US20230153587A1

公开(公告)日：2023-05-18

申请号：US17910739

申请日：2021-03-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven Woo ,  Liji Gopalakrishnan

IPC: G06N3/063 ,  H10B80/00 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06N3/084 ,  H10B80/00

Abstract: A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit. The accelerator die includes a high-bandwidth memory (HBM) interface that allows a host processor to store training data and retrieve inference-model and output data from memory. The accelerator die additionally includes accelerator tiles with a direct, inter-die memory interfaces to a stack of underlying memory banks. The 3-D IC thus supports both HBM memory channels optimized for external access and accelerator-specific memory channels optimized for training and inference.

公开(公告)号：US20230072674A1

公开(公告)日：2023-03-09

申请号：US17800601

申请日：2021-02-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Liji Gopalakrishnan

IPC: G06F3/06

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.