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16 条记录 (耗时 0.025 秒)

    Memory mirroring
    3.
    发明授权
    Memory mirroring 有权

    公开(公告)号：US09798628B2

    公开(公告)日：2017-10-24

    申请号：US14568848

    申请日：2014-12-12

    申请人： Rambus Inc.

    发明人： Steven Woo ,  David Secker ,  Ravindranath Kollipara

    IPC分类号： G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

    CPC分类号： G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

    摘要： Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

    Stacked-Die Neural Network with Integrated High-Bandwidth Memory
    4.
    发明公开
    Stacked-Die Neural Network with Integrated High-Bandwidth Memory 审中-公开

    公开(公告)号：US20230153587A1

    公开(公告)日：2023-05-18

    申请号：US17910739

    申请日：2021-03-23

    申请人： Rambus Inc.

    发明人： Thomas Vogelsang ,  Steven Woo ,  Liji Gopalakrishnan

    IPC分类号： G06N3/063 ,  H10B80/00 ,  G06N3/084

    CPC分类号： G06N3/063 ,  G06N3/084 ,  H10B80/00

    摘要： A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit. The accelerator die includes a high-bandwidth memory (HBM) interface that allows a host processor to store training data and retrieve inference-model and output data from memory. The accelerator die additionally includes accelerator tiles with a direct, inter-die memory interfaces to a stack of underlying memory banks. The 3-D IC thus supports both HBM memory channels optimized for external access and accelerator-specific memory channels optimized for training and inference.

    Module based data transfer
    5.
    发明授权
    Module based data transfer 有权

    公开(公告)号：US10540303B2

    公开(公告)日：2020-01-21

    申请号：US16236971

    申请日：2018-12-31

    申请人： Rambus Inc.

    发明人： Steven Woo ,  David Secker

    IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F3/06 ,  G06F11/00

    摘要： A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.

    FLEXIBLE METADATA ALLOCATION AND CACHING
    8.
    发明公开
    FLEXIBLE METADATA ALLOCATION AND CACHING 审中-公开

    公开(公告)号：US20240013819A1

    公开(公告)日：2024-01-11

    申请号：US18348716

    申请日：2023-07-07

    申请人： Rambus Inc.

    发明人： Taeksang Song ,  Steven Woo ,  Craig Hampel ,  John Eric Linstadt

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1084 ,  G11C7/1006

    摘要： An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.

    Module based data transfer
    10.
    发明授权
    Module based data transfer 有权

    公开(公告)号：US10169257B2

    公开(公告)日：2019-01-01

    申请号：US15048690

    申请日：2016-02-19

    申请人： Rambus Inc.

    发明人： Steven Woo ,  David Secker

    IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F3/06 ,  G06F11/00

    摘要： A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.