公开(公告)号：US20170054019A1

公开(公告)日：2017-02-23

申请号：US15225559

申请日：2016-08-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7816 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and indirect contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.

Abstract translation: 横向双扩散金属氧化物半导体器件包括：P型衬底，外延层，P型高压阱，P型体区，N型阱，隔离氧化物区域，漂移氧化物 区域，栅极，N型接触区域，P型接触区域，顶部源极，底部源极和N型漏极。 P型体区在P型高电压阱和外延层的表面之间并连接。 P型体区域包括在外延层的表面下方并间接接触的峰值浓度区域，其中峰值浓度区域在P型体区域中具有最高的P型杂质浓度。 P型体区域的P型杂质浓度高于预定阈值，以抑制寄生双极晶体管不导通。

公开(公告)号：US09543303B1

公开(公告)日：2017-01-10

申请号：US15136917

申请日：2016-04-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L27/0928 ,  H01L21/76202 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a dual-well complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The dual-well CMOS device includes a PMOS device region and an NMOS device region. Each of the PMOS and NMOS device regions includes a dual-well (which includes a P-well and an N-well), and each of the PMOS and NMOS device regions includes P-type and N-type lightly doped diffusions (PLDD and NLDD) regions respectively in different wells in the dual well. A separation region is located between the PMOS device region and the NMOS device region, for separating the PMOS device region and the NMOS device region. The depth of the separation region is not less than the depth of any of the P-wells and the N-wells in the PMOS device region and the NMOS device region.

Abstract translation: 本发明公开了一种双阱互补金属氧化物半导体（CMOS）器件及其制造方法。 双阱CMOS器件包括PMOS器件区域和NMOS器件区域。 PMOS和NMOS器件区域中的每一个包括双阱（其包括P阱和N阱），并且PMOS和NMOS器件区域中的每一个包括P型和N型轻掺杂扩散（PLDD和 NLDD）区域分别在双井不同井中。 分离区域位于PMOS器件区域和NMOS器件区域之间，用于分离PMOS器件区域和NMOS器件区域。 分离区域的深度不小于PMOS器件区域和NMOS器件区域中的任何P阱和N阱的深度。

公开(公告)号：US11063148B2

公开(公告)日：2021-07-13

申请号：US15909277

申请日：2018-03-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Ching-Yao Yang

IPC: H01L21/8234 ,  H01L21/761 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088

Abstract: A high voltage depletion mode MOS device with adjustable threshold voltage includes: a first conductive type well region; a second conductive type channel region, wherein when the channel region is not depleted, the MOS device is conductive, and when the channel region is depleted, the MOS device is non-conductive; a second conductive type connection region which contacts the channel region; a first conductive type gate, for controlling the conductive condition of the MOS device; a second conductive type lightly doped diffusion region formed under a spacer layer of the gate and contacting the channel region; a second type source region; and a second type drain region contacting the connection region but not contacting the gate; wherein the gate has a first conductive type doping or both a first and a second conductive type doping, and wherein a net doping concentration of the gate is determined by a threshold voltage target.

公开(公告)号：US10943978B2

公开(公告)日：2021-03-09

申请号：US16354140

申请日：2019-03-14

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L21/74

Abstract: An N-type high voltage device includes: a semiconductor layer, a well region, a floating region, a bias region, a body region, a body contact, a gate, a source and a drain. The floating region and the bias region both have P-type conductivity, and both are formed in a drift region in the well region. The bias region is electrically connected with a predetermined bias voltage, and the floating region is electrically floating, to increase a breakdown voltage of the high voltage device and to suppress turning-ON a parasitic transistor in the high voltage device.

公开(公告)号：US10714612B2

公开(公告)日：2020-07-14

申请号：US16232030

申请日：2018-12-25

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, a drain and a conductive connection structure. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region in the operation region. The sub-gate is a rectangle shape extending along a width direction, and in parallel with the gate. A conductive connection structure connects the gate and the sub-gate.

公开(公告)号：US20200220005A1

公开(公告)日：2020-07-09

申请号：US16711383

申请日：2019-12-11

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A high voltage device for use as a lower switch in a power stage of a switching regulator includes at least one lateral diffused metal oxide semiconductor (LDMOS) device and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well, a body region, a gate, a source, and a drain. The SBD includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected to the source, and the Schottky semiconductor layer is in contact with the well.

公开(公告)号：US10680104B2

公开(公告)日：2020-06-09

申请号：US16352766

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L21/266 ,  H01L29/66

Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.

公开(公告)号：US10680059B2

公开(公告)日：2020-06-09

申请号：US16130921

申请日：2018-09-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

公开(公告)号：US20190302822A1

公开(公告)日：2019-10-03

申请号：US16274162

申请日：2019-02-12

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Yu Chen ,  Tsung-Yi Huang ,  Ting-Wei Liao

IPC: G05F3/22 ,  H03K17/22 ,  H03K19/003 ,  H02H9/04

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

公开(公告)号：US10326016B2

公开(公告)日：2019-06-18

申请号：US16038015

申请日：2018-07-17

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.