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公开(公告)号：US11522536B2
公开(公告)日：2022-12-06
申请号：US17568637
申请日：2022-01-04
Applicant: Richtek Technology Corporation
Inventor： Kun-Huang Yu , Chien-Yu Chen , Ting-Wei Liao , Wu-Te Weng , Chien-Wei Chiu , Yong-Zhong Hu , Ta-Yung Yang
IPC: H03K17/00 , H03K17/16 , H03K17/687
Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
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公开(公告)号：US20220157982A1
公开(公告)日：2022-05-19
申请号：US17506422
申请日：2021-10-20
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Kuo-Chin Chiu , Ta-Yung Yang , Chien-Wei Chiu , Wu-Te Weng , Chien-Yu Chen , Chih-Wen Hsiung , Chun-Lung Chang , Kun-Huang Yu , Ting-Wei Liao
IPC: H01L29/78 , H01L29/872 , H01L29/66
Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.
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公开(公告)号：US11876453B2
公开(公告)日：2024-01-16
申请号：US17560761
申请日：2021-12-23
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
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公开(公告)号：US20220238727A1
公开(公告)日：2022-07-28
申请号：US17571401
申请日：2022-01-07
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Wu-Te Weng , Chien-Wei Chiu , Ta-Yung Yang
IPC: H01L29/866 , H01L29/78 , H01L29/06 , H01L29/66
Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.
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公开(公告)号：US20220239224A1
公开(公告)日：2022-07-28
申请号：US17567130
申请日：2022-01-02
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
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Patent Agency Ranking
公开(公告)号：US20220239223A1
公开(公告)日：2022-07-28
申请号：US17560761
申请日：2021-12-23
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ting-Wei Liao , Chien-Yu Chen , Kun-Huang Yu , Chien-Wei Chiu , Ta-Yung Yang
Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
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公开(公告)号：US20220224325A1
公开(公告)日：2022-07-14
申请号：US17568637
申请日：2022-01-04
Applicant: Richtek Technology Corporation
Inventor： Kun-Huang Yu , Chien-Yu Chen , Ting-Wei Liao , Wu-Te Weng , Chien-Wei Chiu , Yong-Zhong Hu , Ta-Yung Yang
IPC: H03K17/16
Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
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公开(公告)号：US20190302822A1
公开(公告)日：2019-10-03
申请号：US16274162
申请日：2019-02-12
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Chien-Yu Chen , Tsung-Yi Huang , Ting-Wei Liao
IPC: G05F3/22 , H03K17/22 , H03K19/003 , H02H9/04
Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.
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公开(公告)号：US20240297067A1
公开(公告)日：2024-09-05
申请号：US18664656
申请日：2024-05-15
Applicant: Richtek Technology Corporation
Inventor： Kun-Huang Yu , Chien-Yu Chen , Ting-Wei Liao , Chih-Wen Hsiung , Chun-Lung Chang , Kuo-Chin Chiu , Wu-Te Weng , Chien-Wei Chiu , Yong-Zhong Hu , Ta-Yung Yang
IPC: H01L21/762 , H01L29/06 , H01L29/423 , H01L29/78
CPC classification number: H01L21/7621 , H01L21/76221 , H01L21/76281 , H01L29/0653 , H01L29/42368 , H01L29/7816
Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
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公开(公告)号：US12062570B2
公开(公告)日：2024-08-13
申请号：US17547829
申请日：2021-12-10
Applicant: Richtek Technology Corporation
Inventor： Kun-Huang Yu , Chien-Yu Chen , Ting-Wei Liao , Chih-Wen Hsiung , Chun-Lung Chang , Kuo-Chin Chiu , Wu-Te Weng , Chien-Wei Chiu , Yong-Zhong Hu , Ta-Yung Yang
IPC: H01L29/78 , H01L21/762 , H01L29/06 , H01L29/423
CPC classification number: H01L21/7621 , H01L21/76221 , H01L21/76281 , H01L29/0653 , H01L29/42368 , H01L29/7816
Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
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