公开(公告)号：US20200044022A1

公开(公告)日：2020-02-06

申请号：US16449350

申请日：2019-06-22

Applicant: Richtek Technology Corporation

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.

公开(公告)号：US20230045843A1

公开(公告)日：2023-02-16

申请号：US17749071

申请日：2022-05-19

Applicant: Richtek Technology Corporation

Inventor： Yu-Ting Yeh ,  Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/765 ,  H01L29/66

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

公开(公告)号：US20220165880A1

公开(公告)日：2022-05-26

申请号：US17666501

申请日：2022-02-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Kun-Huang Yu ,  Ying-Shiou Lin ,  Chu-Feng Chen ,  Chung-Yu Hung ,  Yi-Rong Tu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

公开(公告)号：US10236375B2

公开(公告)日：2019-03-19

申请号：US15889051

申请日：2018-02-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L21/266

Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.

公开(公告)号：US20180331211A1

公开(公告)日：2018-11-15

申请号：US15889051

申请日：2018-02-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.

公开(公告)号：US10680059B2

公开(公告)日：2020-06-09

申请号：US16130921

申请日：2018-09-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

公开(公告)号：US20190131390A1

公开(公告)日：2019-05-02

申请号：US16130921

申请日：2018-09-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

公开(公告)号：US20190096992A1

公开(公告)日：2019-03-28

申请号：US16203669

申请日：2018-11-29

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L21/266 ,  H01L29/10 ,  H01L29/78 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66 ,  H01L21/225 ,  H01L29/40

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

公开(公告)号：US10177220B2

公开(公告)日：2019-01-08

申请号：US15662277

申请日：2017-07-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

公开(公告)号：US09853099B1

公开(公告)日：2017-12-26

申请号：US15490626

申请日：2017-04-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0611 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, a drift buried region and a buried region. A first PN junction is formed between the high voltage well and an upper surface of the substrate. From a cross-section view, along the channel direction, a second PN junction is formed between the drift buried region and the buried region or formed between the high voltage well and the buried region. Along the channel direction, the first PN junction and the second PN junction have respective depths. The depth is defined as a distance extending from the upper face of the epitaxial layer downward along a vertical direction. The depth of the second PN junction is shallower than the depth of the first PN junction.