公开(公告)号：US09459851B2

公开(公告)日：2016-10-04

申请号：US12823244

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/45

CPC分类号： G06F8/4442

摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

摘要翻译： 提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。 这些机制产生一部分代码的调用图。 调用图中的节点和边被加权以生成加权调用图。 然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码 调用图被组合到基于分区的各个高速缓存行。 然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

公开(公告)号：US08862827B2

公开(公告)日：2014-10-14

申请号：US12648667

申请日：2009-12-29

申请人： Brian Flachs ,  Barry L. Minor ,  Mark Richard Nutter

发明人： Brian Flachs ,  Barry L. Minor ,  Mark Richard Nutter

IPC分类号： G06F12/08 ,  G06F9/45

CPC分类号： G06F12/0864 ,  G06F8/4442 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/6082

摘要： A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache manager identifies a corresponding cache location and retrieves the data from the identified cache location. However, when the most recently used effective address fails to match the requested effective address, the cache manager determines whether the requested effective address matches a subsequent effective address stored in the mapped tag vector. When the cache manager determines a match to a subsequent effective address, the cache manager identifies a different cache location corresponding to the subsequent effective address and retrieves the data from the different cache location.

摘要翻译： 缓存管理器接收对数据的请求，其中包括请求的有效地址。 高速缓存管理器确定所请求的有效地址是否匹配存储在映射的标签向量中的最近使用的有效地址。 当最近使用的有效地址与所请求的有效地址匹配时，高速缓存管理器识别对应的高速缓存位置并从所识别的高速缓存位置检索数据。 然而，当最近使用的有效地址不能匹配所请求的有效地址时，高速缓存管理器确定所请求的有效地址是否匹配存储在映射的标签向量中的后续有效地址。 当高速缓存管理器确定与随后的有效地址的匹配时，高速缓存管理器识别与随后的有效地址相对应的不同高速缓存位置，并从不同的高速缓存位置检索数据。

公开(公告)号：US08726252B2

公开(公告)日：2014-05-13

申请号：US13016406

申请日：2011-01-28

申请人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

发明人： Alexandre E. Eichenberger ,  Brian Flachs ,  Dorit Nuzman ,  Ira Rosen ,  Ulrich Weigand ,  Ayal Zaks

IPC分类号： G06F9/45 ,  G06F15/76

CPC分类号： G06F8/456

摘要： A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies “if-then-else” statements that offer opportunity for conditional branch conversion. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original “if-then-else” statements. The processor continues processing next statements inline after all SIMD lanes are complete, while providing speculative and parallel processing capability for multiple data operations of the executable program.

摘要翻译： 单指令多数据（SIMD）信息处理系统（IHS）的编译器标识“if-then-else”语句，为条件分支转换提供机会。 SIMD IHS采用处理器或处理器来执行可执行程序。 在执行期间，处理器生成并更新SIMD通道掩码信息以跟踪和管理执行程序的条件分支循环。 处理器保存分支地址，并使用SIMD通道屏蔽来识别具有不同分支条件的条件分支循环，而不是先前的条件分支循环。 在处理原始“if-then-else”语句的编译代码时，处理器可能会减少SIMD IHS处理时间。 在所有SIMD通道完成之后，处理器继续处理下一个语句，同时为可执行程序的多个数据操作提供推测性和并行处理能力。

公开(公告)号：US08522225B2

公开(公告)日：2013-08-27

申请号：US12823204

申请日：2010-06-25

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K. P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/45

CPC分类号： G06F8/4436 ,  G06F8/433 ,  G06F8/4442

摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

摘要翻译： 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。 此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。 此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预 。

公开(公告)号：US08359435B2

公开(公告)日：2013-01-22

申请号：US12639010

申请日：2009-12-16

申请人： Revital Erez ,  Brian Flachs ,  Mark Richard Nutter ,  John Kevin Patrick O'Brien ,  Ulrich Weigand ,  Ayal Zaks

发明人： Revital Erez ,  Brian Flachs ,  Mark Richard Nutter ,  John Kevin Patrick O'Brien ,  Ulrich Weigand ,  Ayal Zaks

IPC分类号： G06F12/00

CPC分类号： G06F21/52 ,  G06F11/3466 ,  G06F21/53 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based on the profile, an optimized layout of the lines in the code is computed, and the lines of the program are re-ordered in accordance with the optimized layout while continuing to execute the program.

摘要翻译： 一种用于计算的方法包括在具有软件管理的高速缓存的处理器上执行包括可执行代码的多个可缓存行的程序。 在处理器上运行的运行时缓存管理例程用于在执行程序时组合在软件管理的高速缓存中发生的跨线跳转配置文件。 基于该配置文件，计算代码中行的优化布局，并且在继续执行程序的同时根据优化的布局重新排序程序的行。

公开(公告)号：US20120204016A1

公开(公告)日：2012-08-09

申请号：US13443188

申请日：2012-04-10

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F9/318

CPC分类号： G06F8/4436 ,  G06F8/433 ,  G06F8/4442

摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.

摘要翻译： 提供了用于在一部分代码中重写分支指令的机制。 该机制接收一部分具有原始分支指令的源代码。 机制为原始分支指令生成分支存根。 分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。 此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。 此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。 计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预 。

公开(公告)号：US20120198170A1

公开(公告)日：2012-08-02

申请号：US13444890

申请日：2012-04-12

申请人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

发明人： Tong Chen ,  Brian Flachs ,  Brad W. Michael ,  Mark R. Nutter ,  John K.P. O'Brien ,  Kathryn M. O'Brien ,  Tao Zhang

IPC分类号： G06F12/08 ,  G06F9/38

CPC分类号： G06F8/4442 ,  G06F9/3806 ,  G06F12/0875 ,  G06F12/12

摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

摘要翻译： 提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。 机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。 确定当前高速缓存行是否将从指令高速缓存中逐出。 处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。 此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

公开(公告)号：US07689865B2

公开(公告)日：2010-03-30

申请号：US11470478

申请日：2006-09-06

申请人： Heinz Baier ,  Christopher R. Conley ,  Brian Flachs ,  Michael T. Saunders ,  Steven J. Smolski

发明人： Heinz Baier ,  Christopher R. Conley ,  Brian Flachs ,  Michael T. Saunders ,  Steven J. Smolski

IPC分类号： G06F11/00

CPC分类号： G06F11/2236 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572

摘要： A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

摘要翻译： 一种方法，设备，系统和计算机程序产品，用于实现对JTAG（联合测试动作组）IEEE 1149.1能力设备（或被测系统（SUT））的调试过程的高级控制。 Middlesoft Commander在一个JTAG（或JTAG）POD中提供，它连接到执行调试软件的主机系统和SUT。 POD和SUT之间的通信可以通过桥接POD和SUT之间的连接的一对JTAG接口来实现。 Middlesoft Commander包括代码，使Middlesoft Commander能够将从主机系统（或由主机系统）生成的高级命令（调试数据包）转换为JTAG命令。 这些JTAG命令被转发到SUT。 Middlesoft Commander还包括使Middlesoft Commander将从SUT接收到的JTAG数据转换为主机系统可识别的命令的代码。

公开(公告)号：US07610531B2

公开(公告)日：2009-10-27

申请号：US11531287

申请日：2006-09-13

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

摘要翻译： 提供了修改测试模式以控制电源噪声的机制。 修改测试图形波形的测试序列中的状态序列的一部分被修改，以便实现近似标称电路电压的电路电压，例如片上电压，例如通过施加其它部分产生的电压 的相同或不同测试序列中的状态序列。 例如，保持状态周期或移位扫描状态周期可以在测试模式波形中的测试状态周期之前被插入或移除。 插入/移除将测试状态周期的发生移动到测试图形波形内，以便调整测试状态周期的电压响应，使得它们更接近于额定电压响应。 以这种方式，可以消除由于电压源中的噪声引起的错误故障。

公开(公告)号：US20090204781A1

公开(公告)日：2009-08-13

申请号：US12429676

申请日：2009-04-24

申请人： Adam P. Burns ,  Michael N. Day ,  Brian Flachs ,  H. Peter Hofstee ,  Charles R. Johns ,  John Liberty

发明人： Adam P. Burns ,  Michael N. Day ,  Brian Flachs ,  H. Peter Hofstee ,  Charles R. Johns ,  John Liberty

IPC分类号： G06F12/00 ,  G06F3/00 ,  G06F12/02 ,  G06F15/00

CPC分类号： G06F12/0661 ,  G06F12/0223

摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

摘要翻译： 提供了用于限制处理器的本地存储器的大小的系统。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。