公开(公告)号：US20210320075A1

公开(公告)日：2021-10-14

申请号：US17357040

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI ,  Ramy Nashed Bassely SAID

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first metallic plates. First bonding pads including a respective one of the first metallic plates are formed. A first polymer material layer can be formed over the first bonding pads. A second semiconductor die including second bonding pads is bonded to the first bonding pads to form a bonded assembly.

公开(公告)号：US20210217716A1

公开(公告)日：2021-07-15

申请号：US16742213

申请日：2020-01-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11526 ,  H01L25/00

Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：US20210159216A1

公开(公告)日：2021-05-27

申请号：US16694438

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L25/00 ,  H01L27/06

Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.

公开(公告)号：US20200343161A1

公开(公告)日：2020-10-29

申请号：US16391632

申请日：2019-04-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/18 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

公开(公告)号：US20200006374A1

公开(公告)日：2020-01-02

申请号：US16019904

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Jayavel PACHAMUTHU

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.