公开(公告)号：US20220093644A1

公开(公告)日：2022-03-24

申请号：US17543987

申请日：2021-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Kartik SONDHI ,  Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/423

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

公开(公告)号：US20210028135A1

公开(公告)日：2021-01-28

申请号：US16851908

申请日：2020-04-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L23/00 ,  H01L25/18

Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

公开(公告)号：US20230018394A1

公开(公告)日：2023-01-19

申请号：US17378196

申请日：2021-07-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Ramy Nashed Bassely SAID

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/06

Abstract: A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.

公开(公告)号：US20220285386A1

公开(公告)日：2022-09-08

申请号：US17192463

申请日：2021-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

公开(公告)号：US20220254797A1

公开(公告)日：2022-08-11

申请号：US17169987

申请日：2021-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Dana LEE

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

公开(公告)号：US20210320075A1

公开(公告)日：2021-10-14

申请号：US17357040

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Masaaki HIGASHITANI ,  Ramy Nashed Bassely SAID

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first metallic plates. First bonding pads including a respective one of the first metallic plates are formed. A first polymer material layer can be formed over the first bonding pads. A second semiconductor die including second bonding pads is bonded to the first bonding pads to form a bonded assembly.

公开(公告)号：US20240105623A1

公开(公告)日：2024-03-28

申请号：US17934685

申请日：2022-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Lito De La RAMA

IPC: H01L23/535 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

公开(公告)号：US20220189993A1

公开(公告)日：2022-06-16

申请号：US17122360

申请日：2020-12-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan TIRUKKONDA ,  Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.

公开(公告)号：US20220139960A1

公开(公告)日：2022-05-05

申请号：US17579183

申请日：2022-01-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L27/11597 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.

公开(公告)号：US20220059462A1

公开(公告)日：2022-02-24

申请号：US17000934

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Yao-Sheng LEE

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor structure includes first metal lines located above at least one semiconductor device, and a continuous metal organic framework (MOF) material layer including lower MOF portions that are located between neighboring pairs of first metal lines and an upper MOF matrix portion that continuously extends over the first metal lines and connected to each of the lower MOF portions.