公开(公告)号：US20210035999A1

公开(公告)日：2021-02-04

申请号：US16556919

申请日：2019-08-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Jayavel PACHAMUTHU

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

公开(公告)号：US20200006374A1

公开(公告)日：2020-01-02

申请号：US16019904

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Jayavel PACHAMUTHU

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US20210036004A1

公开(公告)日：2021-02-04

申请号：US16583906

申请日：2019-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takumi MORIYAMA ,  Yasushi DOWAKI ,  Yuki KASAI ,  Satoshi SHIMIZU ,  Jayavel PACHAMUTHU

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.

公开(公告)号：US20200006364A1

公开(公告)日：2020-01-02

申请号：US16019961

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Jayavel PACHAMUTHU

IPC: H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US20170365613A1

公开(公告)日：2017-12-21

申请号：US15279959

申请日：2016-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Marika GUNJI-YONEOKA ,  Atsushi SUYAMA ,  Jayavel PACHAMUTHU ,  Tsuyoshi HADA ,  Daewung KANG ,  Murshed CHOWDHURY ,  James KAI ,  Hiro KINOSHITA ,  Tomoyuki OBU ,  Luckshitha Suriyasena LIYANAGE

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

公开(公告)号：US20210036003A1

公开(公告)日：2021-02-04

申请号：US16526128

申请日：2019-07-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jayavel PACHAMUTHU ,  Hiroyuki KINOSHITA ,  Marika GUNJI-YONEOKA ,  Tadashi NAKAMURA ,  Tomohiro OGINOE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/45 ,  H01L29/167 ,  H01L29/04 ,  H01L21/28 ,  H01L21/02 ,  H01L21/285

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers.

公开(公告)号：US20210035998A1

公开(公告)日：2021-02-04

申请号：US16556854

申请日：2019-08-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Jayavel PACHAMUTHU

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

公开(公告)号：US20180108671A1

公开(公告)日：2018-04-19

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo YU ,  Jayavel PACHAMUTHU ,  Jongsun SEL ,  Tuan PHAM ,  Cheng-Chung CHU ,  Yao-Sheng LEE ,  Kensuke YAMAGUCHI ,  Masanori TERAHARA ,  Shuji MINAGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US20170373087A1

公开(公告)日：2017-12-28

申请号：US15195377

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitoshi ITO ,  Masaaki HIGASHITANI ,  Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

公开(公告)号：US20170373078A1

公开(公告)日：2017-12-28

申请号：US15195446

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM ,  Fumitoshi ITO ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/22 ,  H01L27/11519 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.