公开(公告)号：US11500771B2

公开(公告)日：2022-11-15

申请号：US17154838

申请日：2021-01-21

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F11/14 ,  G06F12/0804

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.

公开(公告)号：US11334248B2

公开(公告)日：2022-05-17

申请号：US16922317

申请日：2020-07-07

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

Abstract: An electronic device includes a storage device having migration performance of an improved speed. The storage device includes a memory device including a normal memory block and a buffer memory block for temporarily storing data that is to be migrated to the normal memory block and a memory controller configured to control the memory device to migrate the data, which is stored in the buffer memory block, to the normal memory block in response to a migration request received from a host, the memory controller changing a target memory block, in which the data is to be stored, from a first memory block to a second memory block according to whether an operation corresponding to the migration request is delayed or not, while migrating the data to the normal memory block, the first memory block and the second memory block being included in the normal memory block.

公开(公告)号：US11237954B2

公开(公告)日：2022-02-01

申请号：US16895019

申请日：2020-06-08

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/14 ,  G06F1/12 ,  G06F12/0873

Abstract: Provided herein may be a controller and a data storage system having the controller. The controller may include a mapping time generator configured to generate a first mapping time at which a logical block address and a physical block address are mapped to each other, an internal memory configured to store first address mapping information including an address map, and the first mapping time, a host interface configured to transmit the first address mapping information to a host, and receive second address mapping information from the host, and a central processing unit configured to generate the address map, store the first address mapping information in the internal memory, compare a second mapping time included in the second address mapping information with the first mapping time, and select a read mode based on a result of the comparison.

公开(公告)号：US11113203B2

公开(公告)日：2021-09-07

申请号：US16673620

申请日：2019-11-04

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/0891 ,  G06F12/0873 ,  G11C11/409 ,  G06F13/16 ,  G06F12/02

Abstract: Provided herein may be a controller and a method of operating the same. The controller for controlling an operation of a semiconductor memory device may include a request analyzer, a map cache controller, and a command generator. The request analyzer receives a first request from a host. The map cache controller generates a first mapping segment including a plurality of mapping entries and a flag bit based on the first request, and sets a value of the flag bit depending on whether data corresponding to the first mapping segment is random data or sequential data. The command generator generates a program command for programming the mapping segment.

公开(公告)号：US10963399B2

公开(公告)日：2021-03-30

申请号：US16592359

申请日：2019-10-03

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/109 ,  G06F12/126

Abstract: A memory system may include a storage device and a controller. The storage device may include a non-volatile memory device. The controller may include a device memory. The controller may control operations of the non-volatile memory device in accordance with a request of a host device. wherein the controller includes a map data management circuit configured to cache one or more segments from a plurality of map segment groups stored in the storage device, each segment having information including a reference count and mapping relationships between logical addresses and physical addresses, detect, among the one or more cached segments, an upload target segment in which the reference count is greater than a predetermined count and transmit, when a predetermined number or greater of upload target segments are detected within a first map segment group, the predetermined number or greater of upload target segments to the host device.

公开(公告)号：US10936508B2

公开(公告)日：2021-03-02

申请号：US16569536

申请日：2019-09-12

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F12/1009

Abstract: A memory controller may include: a map data processor configured to receive original map data segments from a memory device and generate a mode signal; an original map data storage configured to sequentially store the original map data segments in source storage areas corresponding to source addresses; a converted map data storage configured to store the original map data segments in target storage areas corresponding to target addresses; and a map data converter configured to control the converted map data storage such that, when any one original map data segment is stored in a first target storage area corresponding to a first target address, an original map data segment subsequent to the any one original map data segment is stored in a second target storage area corresponding to a second target address obtained by adding a predetermined offset to the first target address.

公开(公告)号：US10817192B2

公开(公告)日：2020-10-27

申请号：US15980350

申请日：2018-05-15

Applicant: SK hynix Inc.

Inventor： Jung Woo Kim ,  Eu Joon Byun

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06

Abstract: A data storage apparatus includes a nonvolatile memory device including a plurality of memory block groups and a controller configured to, when use of a first memory block group selected from the plurality of memory block groups is completed, select a second memory block group to be used next from among remaining memory block groups, excluding the first memory block group, of the plurality of memory block groups based on interleaving indexes of the remaining memory block groups.

公开(公告)号：US12182395B2

公开(公告)日：2024-12-31

申请号：US18085449

申请日：2022-12-20

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06

Abstract: An electronic device includes an external device configured to determine a first performance index on the basis of at least one of a power level and a temperature signal, to put the first performance index into a command, and to output the command. The electronic device also includes a storage component including a plurality of memory dies. The electronic device further includes a memory controller configured to provide the temperature signal to the external device at a set transmission period, and to control the storage component to process the command by simultaneously operating the number of memory dies corresponding to the first performance index as the command is received.

公开(公告)号：US11960765B2

公开(公告)日：2024-04-16

申请号：US17532789

申请日：2021-11-22

Applicant: SK hynix Inc.

Inventor： Hye Mi Kang ,  Eu Joon Byun

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0673

Abstract: The present technology relates to a storage device. According to the present technology, a memory controller controlling a memory device including a plurality of memory blocks may include an operation controller and a lifetime information controller. The operation controller may control the memory device to receive a write request from a host and perform a write operation on a selected memory block among the plurality of memory blocks. The lifetime information controller may generate lifetime information including a lifetime level of the selected memory block based on an erase and write count of the selected memory block.

公开(公告)号：US11954351B2

公开(公告)日：2024-04-09

申请号：US17728739

申请日：2022-04-25

Applicant: SK hynix Inc.

Inventor： Eu Joon Byun

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0641 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.