Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator

    公开(公告)号:US10862503B2

    公开(公告)日:2020-12-08

    申请号:US16702246

    申请日:2019-12-03

    Abstract: A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

    High speed data weighted averaging architecture

    公开(公告)号:US10211850B1

    公开(公告)日:2019-02-19

    申请号:US16034467

    申请日:2018-07-13

    Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

    High speed data weighted averaging architecture

    公开(公告)号:US10050640B1

    公开(公告)日:2018-08-14

    申请号:US15864233

    申请日:2018-01-08

    Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

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