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41.
公开(公告)号:US10862503B2
公开(公告)日:2020-12-08
申请号:US16702246
申请日:2019-12-03
Applicant: STMicroelectronics International N.V.
Inventor: Ankur Bal , Rupesh Singh
Abstract: A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.
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公开(公告)号:US10211850B1
公开(公告)日:2019-02-19
申请号:US16034467
申请日:2018-07-13
Applicant: STMicroelectronics International N.V.
Inventor: Ankur Bal , Rupesh Singh
Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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公开(公告)号:US10050640B1
公开(公告)日:2018-08-14
申请号:US15864233
申请日:2018-01-08
Applicant: STMicroelectronics International N.V.
Inventor: Ankur Bal , Rupesh Singh
Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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公开(公告)号:US09685150B2
公开(公告)日:2017-06-20
申请号:US14271128
申请日:2014-05-06
Applicant: STMicroelectronics International N.V.
Inventor: Ankur Bal , Anupam Jain , Rakhel Kumar Parida
IPC: H04B15/00 , G10K11/00 , H04L25/03 , H04L27/26 , G10L21/0208 , G10L21/0232 , H04L5/00
CPC classification number: G10K11/002 , G10L21/0208 , G10L21/0232 , H04L5/0008 , H04L25/03159 , H04L27/2649 , H04L2025/03414
Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.
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