公开(公告)号：US11250309B2

公开(公告)日：2022-02-15

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063 ,  H01L27/02 ,  G11C11/54 ,  H01L29/423 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US11223386B2

公开(公告)日：2022-01-11

申请号：US16878084

申请日：2020-05-19

Applicant: STMicroelectronics SA

Inventor： Mohammed Tmimi ,  Philippe Galy

IPC: H04B3/02 ,  H04L27/20

Abstract: Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.

公开(公告)号：US11037938B2

公开(公告)日：2021-06-15

申请号：US16594311

申请日：2019-10-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: G11C17/00 ,  H01L27/112 ,  H01L29/417

Abstract: An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.

公开(公告)号：US10211201B2

公开(公告)日：2019-02-19

申请号：US15914387

申请日：2018-03-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/45

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US10128242B2

公开(公告)日：2018-11-13

申请号：US15804669

申请日：2017-11-06

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US10096708B2

公开(公告)日：2018-10-09

申请号：US15230699

申请日：2016-08-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/78 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L29/66 ,  H01L21/74 ,  H01L29/786

Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

公开(公告)号：US20180276526A1

公开(公告)日：2018-09-27

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  H01L29/42376 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US20180197848A1

公开(公告)日：2018-07-12

申请号：US15914387

申请日：2018-03-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US09991173B2

公开(公告)日：2018-06-05

申请号：US14155891

申请日：2014-01-15

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H01L21/8249 ,  H01L29/747 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

CPC classification number: H01L21/8249 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/747 ,  H01L29/87

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate, thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

公开(公告)号：US20180012965A1

公开(公告)日：2018-01-11

申请号：US15427656

申请日：2017-02-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/36 ,  H01L29/786

CPC classification number: H01L29/36 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.