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公开(公告)号：US11924545B2
公开(公告)日：2024-03-05
申请号：US17941000
申请日：2022-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Yibing Michelle Wang , Gregory Waligorski , Qiang Zhang
IPC: H04N23/00 , G06T7/521 , H04N23/667
CPC classification number: H04N23/667 , G06T7/521 , H04N2213/003
Abstract: Two-dimensional (2D) color information and 3D-depth information are concurrently obtained from a 2D pixel array. The 2D pixel array is arranged in a first group of a plurality of rows. A second group of rows of the array are operable to generate 2D-color information and pixels of a third group of the array are operable to generate 3D-depth information. The first group of rows comprises a first number of rows, the second group of rows comprises a second number of rows that is equal to or less than the first number of rows, and the third group of rows comprises a third number of rows that is equal to or less than the second number of rows. In an alternating manner, 2D-color information is received from a row selected from the second group of rows and 3D-depth information is received from a row selected from the third group of rows.
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公开(公告)号：US11880760B2
公开(公告)日：2024-01-23
申请号：US16840172
申请日：2020-04-03
Applicant: Samsung Electronics Co., Ltd.
CPC classification number: G06N3/063 , G06F9/3001 , G06F9/30032 , G06F13/1668
Abstract: A processor to perform inference on deep learning neural network models. In some embodiments, the process includes: a first tile, a second tile, a memory, and a bus, the bus being connected to: the memory, the first tile, and the second tile, the first tile including: a first weight register, a second weight register, an activations cache, a shuffler, an activations buffer, a first multiplier, and a second multiplier, the activations buffer being configured to include: a first queue connected to the first multiplier, and a second queue connected to the second multiplier, the activations cache including a plurality of independent lanes, each of the independent lanes being randomly accessible, the first tile being configured: to receive a tensor including a plurality of two-dimensional arrays, each representing one color component of the image; and to perform a convolution of a kernel with one of the two-dimensional arrays.
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公开(公告)号：US11783161B2
公开(公告)日：2023-10-10
申请号：US16446610
申请日：2019-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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公开(公告)号：US11775802B2
公开(公告)日：2023-10-03
申请号：US16552945
申请日：2019-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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公开(公告)号：US11775801B2
公开(公告)日：2023-10-03
申请号：US16552850
申请日：2019-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
CPC classification number: G06N3/04 , G06F17/153 , G06F17/16 , G06N3/08 , G06T9/002 , G06F9/3001
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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Patent Agency Ranking
公开(公告)号：US11360930B2
公开(公告)日：2022-06-14
申请号：US15916189
申请日：2018-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Yibing Michelle Wang
IPC: G06F15/173 , G06F17/16 , G06F7/533 , G06F7/544 , G06F13/16 , G06N3/08 , G06F7/57 , G06F9/38 , G06F17/15
Abstract: A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.
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公开(公告)号：US11153551B2
公开(公告)日：2021-10-19
申请号：US16773505
申请日：2020-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Yibing Michelle Wang , Peter Deane
IPC: H04N13/257 , H04N13/254 , G01B11/25 , H04N13/296 , H04N13/271 , G03B35/02
Abstract: An apparatus and a method are provided. The apparatus includes a light source configured to project light in a changing pattern that reduces the light's noticeability; collection optics through which light passes and forms an epipolar plane with the light source; and an image sensor configured to receive light passed through the collection optics to acquire image information and depth information simultaneously. The method includes projecting light by a light source in a changing pattern that reduces the light's noticeability; passing light through collection optics and forming an epipolar plane between the collection optics and the light source; and receiving in an image sensor light passed through the collection optics to acquire image information and depth information simultaneously.
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公开(公告)号：US10893227B2
公开(公告)日：2021-01-12
申请号：US16549577
申请日：2019-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yibing Michelle Wang , Ilia Ovsiannikov
Abstract: Using the same image sensor to capture a two-dimensional (2D) image and three-dimensional (3D) depth measurements for a 3D object. A laser point-scans the surface of the object with light spots, which are detected by a pixel array in the image sensor to generate the 3D depth profile of the object using triangulation. Each row of pixels in the pixel array forms an epipolar line of the corresponding laser scan line. Timestamping provides a correspondence between the pixel location of a captured light spot and the respective scan angle of the laser to remove any ambiguity in triangulation. An Analog-to-Digital Converter (ADC) in the image sensor operates as a Time-to-Digital (TDC) converter to generate timestamps. A timestamp calibration circuit is provided on-board to record the propagation delay of each column of pixels in the pixel array and to provide necessary corrections to the timestamp values generated during 3D depth measurements.
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公开(公告)号：US20200349420A1
公开(公告)日：2020-11-05
申请号：US16840172
申请日：2020-04-03
Applicant: Samsung Electronics Co., Ltd.
Abstract: A processor to perform inference on deep learning neural network models. In some embodiments, the process includes: a first tile, a second tile, a memory, and a bus, the bus being connected to: the memory, the first tile, and the second tile, the first tile including: a first weight register, a second weight register, an activations cache, a shuffler, an activations buffer, a first multiplier, and a second multiplier, the activations buffer being configured to include: a first queue connected to the first multiplier, and a second queue connected to the second multiplier, the activations cache including a plurality of independent lanes, each of the independent lanes being randomly accessible, the first tile being configured: to receive a tensor including a plurality of two-dimensional arrays, each representing one color component of the image; and to perform a convolution of a kernel with one of the two-dimensional arrays.
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公开(公告)号：US20200026980A1
公开(公告)日：2020-01-23
申请号：US16552945
申请日：2019-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilia Ovsiannikov , Ali Shafiee Ardestani , Joseph H. Hassoun , Lei Wang , Sehwan Lee , JoonHo Song , Jun-Woo Jang , Yibing Michelle Wang , Yuecheng Li
Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.
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