公开(公告)号：US20110180803A1

公开(公告)日：2011-07-28

申请号：US12929453

申请日：2011-01-26

Applicant: Eok-su Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Kyung-bae Park

Inventor： Eok-su Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Kyung-bae Park

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696

Abstract: Thin film transistors (TFTs) and methods of manufacturing the same. A TFT may include a floating channel on a surface of a channel and spaced apart from a source and a drain, and an insulating layer formed on the floating channel and designed to determine a distance between the floating channel and the source or the drain.

Abstract translation: 薄膜晶体管（TFT）及其制造方法。 TFT可以包括在沟道的表面上并与源极和漏极间隔开的浮动沟道，以及形成在浮动沟道上并被设计成确定浮动沟道与源极或漏极之间的距离的绝缘层。

公开(公告)号：US07943985B2

公开(公告)日：2011-05-17

申请号：US12219661

申请日：2008-07-25

Applicant: Tae-sang Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Tae-sang Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/02631

Abstract: Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the channel layer by placing an oxidizing material in contact with the surface of the channel layer, reducing carriers on the surface of the channel layer. Due to the oxidizing agent treatment of the surface of the channel layer, excessive carriers that are generated naturally, or during the manufacturing process, may be more effectively controlled.

Abstract translation: 提供氧化物半导体薄膜晶体管（TFT）及其制造方法。 所述方法包括在衬底上形成沟道层，在沟道层的相对侧形成源极和漏极，并且通过将氧化材料与沟道层的表面相接触来氧化沟道层的表面， 通道层的表面。 由于氧化剂处理通道层的表面，可以更有效地控制天然产生的过量载体或制造过程中产生的过量载体。

公开(公告)号：US07851802B2

公开(公告)日：2010-12-14

申请号：US12219265

申请日：2008-07-18

Applicant: Kyung-bae Park ,  Seon-mi Yoon ,  Sang-yoon Lee ,  Jae-young Choi ,  Hyeon-jin Shin ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Kyung-bae Park ,  Seon-mi Yoon ,  Sang-yoon Lee ,  Jae-young Choi ,  Hyeon-jin Shin ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L31/036

CPC classification number: H01L21/02675 ,  H01L21/02532 ,  H01L29/66765 ,  Y10S977/762 ,  Y10S977/778

Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.

Abstract translation: 示例性实施例涉及由多晶硅（Si）薄膜形成的多晶硅（Si）薄膜，薄膜晶体管（TFT）及其制造方法。 多晶Si薄膜的制造方法包括在基板上形成由非晶Si形成的有源层，在有源层上涂覆金纳米棒，并将红外线照射到金纳米棒上以结晶活性层。

公开(公告)号：US20100127257A1

公开(公告)日：2010-05-27

申请号：US12656256

申请日：2010-01-22

Applicant: Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: Provided is a method of manufacturing a ZnO-based thin film transistor (TFT). The method may include forming source and drain electrodes using one or two wet etchings. A tin (Sn) oxide, a fluoride, or a chloride having relatively stable bonding energy against plasma may be included in a channel layer. Because the source and drain electrodes are formed by wet etching, damage to the channel layer and an oxygen vacancy may be prevented or reduced. Because the material having higher bonding energy is distributed in the channel layer, damage to the channel layer occurring when a passivation layer is formed may be prevented or reduced.

公开(公告)号：US20100012942A1

公开(公告)日：2010-01-21

申请号：US12314212

申请日：2008-12-05

Applicant: Myung-kwan Ryu ,  Kyung-bae Park ,  Sang-yoon Lee ,  Jang-yeon Kwon ,  Byung-wook Yoo ,  Tae-sang Kim ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Myung-kwan Ryu ,  Kyung-bae Park ,  Sang-yoon Lee ,  Jang-yeon Kwon ,  Byung-wook Yoo ,  Tae-sang Kim ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/78624 ,  H01L29/66765

Abstract: Provided may be a Poly-Si thin film transistor (TFT) and a method of manufacturing the same. The Poly-Si TFT may include a first Poly-Si layer on an active layer formed of Poly-Si and doped with a low concentration; and a second Poly-Si layer on the first Poly-Si layer and doped with the same concentration as the first Poly-Si layer or with a higher concentration than the first Poly-Si layer, wherein lightly doped drain (LDD) regions capable of reducing leakage current may be formed in inner end portions of the first Poly-Si layer.

Abstract translation: 提供可以是多晶硅薄膜晶体管（TFT）及其制造方法。 多晶硅TFT可以包括由多晶硅形成并掺杂低浓度的有源层上的第一多晶硅层; 和在第一多晶硅层上掺杂与第一多晶硅层相同的浓度或具有比第一多晶硅层更高的浓度的第二多晶硅层，其中能够 可以在第一多晶硅层的内端部形成减少漏电流。

公开(公告)号：US07638360B2

公开(公告)日：2009-12-29

申请号：US11960567

申请日：2007-12-19

Applicant: Myung-kwan Ryu ,  Jun-seong Kim ,  Sang-yoon Lee ,  Euk-che Hwang ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

Inventor： Myung-kwan Ryu ,  Jun-seong Kim ,  Sang-yoon Lee ,  Euk-che Hwang ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

IPC: H01L21/00

CPC classification number: H01L29/7869

Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near THE surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.

Abstract translation: 这里提供了一种ZnO基薄膜晶体管（TFT），以及TFT的制造方法。 ZnO基TFT具有包含ZnO和ZnCl的沟道层，其中ZnCl相对于等离子体具有比ZnO高的结合能。 ZnCl是通过整个沟道层形成的，具体地形成在沟道层表面附近的区域。 由于ZnCl强度足够暴露于等离子体蚀刻气体时不会分解，因此可以防止载流子浓度的增加。 ZnCl在沟道层中的分布可能是由于在沟道层图案化期间在等离子体气体中包含氯（Cl）。

公开(公告)号：US20080197413A1

公开(公告)日：2008-08-21

申请号：US12032007

申请日：2008-02-15

Applicant: Ji-sim Jung ,  Myung-kwan Ryu ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Min-koo Han ,  Sang-yoon Lee ,  Joong-hyun Park ,  Sang-myeon Han ,  Sun-jae Kim

Inventor： Ji-sim Jung ,  Myung-kwan Ryu ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Min-koo Han ,  Sang-yoon Lee ,  Joong-hyun Park ,  Sang-myeon Han ,  Sun-jae Kim

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78621 ,  H01L29/42384 ,  H01L2029/7863

Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a lower structure; a semiconductor layer formed on the lower structure and including a plurality of doping regions; a first insulating layer and a second insulating layer formed on the semiconductor layer and separated from each other; a third insulating layer formed on the first insulating layer and the second insulating layer; and a gate electrode layer formed between regions of the third insulating layer respectively corresponding to the first insulating layer and the second insulating layer.

Abstract translation: 提供一种薄膜晶体管及其制造方法。 薄膜晶体管包括：下部结构; 半导体层，形成在所述下部结构上并且包括多个掺杂区域; 形成在所述半导体层上并分离的第一绝缘层和第二绝缘层; 形成在所述第一绝缘层和所述第二绝缘层上的第三绝缘层; 以及在第三绝缘层的分别对应于第一绝缘层和第二绝缘层的区域之间形成的栅极电极层。

公开(公告)号：US5254999A

公开(公告)日：1993-10-19

申请号：US8565

申请日：1993-01-22

Applicant: Sang-yoon Lee

Inventor： Sang-yoon Lee

IPC: G01S7/292 ,  G01S7/298 ,  G01S13/66

CPC classification number: G01S7/2923

Abstract: A video signal processor for a radar system includes A/D converters for receiving radar signals to digitize the signals at a predetermined speed, direct averagers for writing signals included in the predetermined size of azimuth among the digitized radar signals into different memories according to the azimuths and for averaging signals corresponding to the same range gates, cell average processors having a microcomputer and a RAM for cell-averaging the output of the direct averagers with the processing program down-loaded from a main controller, an extractor for extracting only target data from the output of one of the cell average processors, a radar video processor controller for generating various control signals, and a communication processor for performing the data transmission and reception between the main controller and the radar video processor controller of the radar system.

Abstract translation: 用于雷达系统的视频信号处理器包括用于接收雷达信号以将数字化为预定速度的信号的A / D转换器，用于根据方位角将数字化雷达信号中包含在预定尺寸方位角的信号写入不同存储器的直接平均器 并且对于与相同范围门对应的平均信号，具有微计算机的单元平均处理器和用于从主控制器下载的处理程序对直接平均器的输出进行单元平均的RAM的单元平均处理器，用于从主控制器提取目标数据的提取器 小区平均处理器之一的输出，用于产生各种控制信号的雷达视频处理器控制器，以及用于在雷达系统的主控制器和雷达视频处理器控制器之间执行数据发送和接收的通信处理器。

公开(公告)号：US09184300B2

公开(公告)日：2015-11-10

申请号：US13588462

申请日：2012-08-17

Applicant: Kyoung-seok Son ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Hyun-suk Kim ,  Joon-seok Park ,  Jong-baek Seon ,  Sang-yoon Lee

Inventor： Kyoung-seok Son ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Hyun-suk Kim ,  Joon-seok Park ,  Jong-baek Seon ,  Sang-yoon Lee

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/7869

Abstract: A transistor may include a hole blocking layer between a channel layer including oxynitride and an electrode electrically connected to the channel layer. The hole blocking layer may be disposed in a region between the channel layer and at least one of a source electrode and a drain electrode. The channel layer may include, for example, zinc oxynitride (ZnON). A valence band maximum energy level of the hole blocking layer may be lower than a valence band maximum energy level of the channel layer.

Abstract translation: 晶体管可以包括在包括氮氧化物的沟道层和电连接到沟道层的电极之间的空穴阻挡层。 空穴阻挡层可以设置在沟道层与源电极和漏电极中的至少一个之间的区域中。 沟道层可以包括例如氮氧化锌（ZnON）。 空穴阻挡层的价带最大能级可以低于沟道层的价带最大能级。

公开(公告)号：US09099561B2

公开(公告)日：2015-08-04

申请号：US13489888

申请日：2012-06-06

Applicant: Hyun-suk Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Jong-baek Seon ,  Kyoung-seok Son ,  Won-mook Choi ,  Joon-seok Park ,  Mi-jeong Song

Inventor： Hyun-suk Kim ,  Sang-yoon Lee ,  Myung-kwan Ryu ,  Tae-sang Kim ,  Jong-baek Seon ,  Kyoung-seok Son ,  Won-mook Choi ,  Joon-seok Park ,  Mi-jeong Song

IPC: H01L29/786

CPC classification number: H01L29/78633 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869

Abstract: A transistor may include a light-blocking layer that blocks light incident on a channel layer. The light-blocking layer may include a carbon-based material. The carbon-based material may include graphene oxide, graphite oxide, graphene or carbon nanotube (CNT). The light-blocking layer may be between a gate and at least one of the channel layer, a source and a drain.

Abstract translation: 晶体管可以包括阻挡入射在沟道层上的光的遮光层。 遮光层可以包括碳基材料。 碳基材料可以包括氧化石墨烯，氧化石墨，石墨烯或碳纳米管（CNT）。 遮光层可以在栅极和沟道层，源极和漏极中的至少一个之间。