公开(公告)号：US07119619B2

公开(公告)日：2006-10-10

申请号：US11037527

申请日：2005-01-18

申请人： Abbas Komijani ,  Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

发明人： Abbas Komijani ,  Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

IPC分类号： H03F3/26

CPC分类号： H03F3/265 ,  H03F1/223 ,  H03F3/423 ,  H03F3/602 ,  H03F3/604 ,  H03F2200/372 ,  H03F2200/421 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/541

摘要： Reconfigurable distributed active transformers are provided. The exemplary embodiments provided allow changing of the effective number and configuration of the primary and secondary windings, where the distributed active transformer structures can be reconfigured dynamically to control the output power levels, allow operation at multiple frequency bands, maintain a high performance across multiple channels, and sustain desired characteristics across process, temperature and other environmental variations. Integration of the distributed active transformer power amplifiers and a low noise amplifier on a semiconductor substrate can also be provided.

公开(公告)号：US06888396B2

公开(公告)日：2005-05-03

申请号：US10385769

申请日：2003-03-11

申请人： Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

发明人： Seyed-Ali Hajimiri ,  Scott D. Kee ,  Ichiri Aoki

IPC分类号： H03F1/22 ,  H03F3/42 ,  H03F3/45 ,  H03K17/687

CPC分类号： H03F3/423 ,  H03F1/22 ,  H03F1/223 ,  H03F1/226 ,  H03F3/42 ,  H03F3/45179 ,  H03F2203/45301 ,  H03F2203/45394 ,  Y10T307/832

摘要： A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

摘要翻译： 提供了具有改善的耐受电压的共源共栅电路。 共源共栅电路包括三个或更多个晶体管，例如MOSFET晶体管。 每个晶体管具有诸如栅极的控制端子和诸如漏极和源极的两个导电端子。 导通端子串联在两个输出端子之间，例如每个晶体管的漏极耦合到另一个晶体管的源极。 向第一晶体管的栅极提供信号输入。 将两个或更多个控制电压源（例如DC偏置电压）提供给剩余晶体管的栅极。 选择DC偏置电压以便将每个晶体管两端的电压保持在低于击穿电压电平的电平。