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公开(公告)号:US20130271092A1
公开(公告)日:2013-10-17
申请号:US13992717
申请日:2011-12-30
申请人: Shekhar Y. Borkar
发明人: Shekhar Y. Borkar
IPC分类号: H02J7/00
摘要: An ultra-capacitor may replace a rechargeable battery in consumer applications where the appliance usage is not prolonged. That is, if the usage is intermittent, the ultra-capacitor can quickly recharge between consecutive uses. Especially for those applications where an appliance spends most of the time on a charging cradle ultra-capacitor may efficiently replace batteries in appliances.
摘要翻译: 超级电容器可以在消费者应用中替换可再充电电池,其中电器使用不会延长。 也就是说,如果使用是间歇性的,超级电容器可以在连续使用之间快速充电。 特别是对于家用电器大部分时间用于充电座的应用,超级电容器可以有效地更换电器中的电池。
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公开(公告)号:US20100328946A1
公开(公告)日:2010-12-30
申请号:US12493023
申请日:2009-06-26
IPC分类号: F21V21/00
CPC分类号: H05B33/0815 , F21K9/232 , F21K9/233 , F21K9/235 , F21K9/238 , F21V3/02 , F21Y2101/00 , F21Y2113/13 , F21Y2115/10 , H05B33/0818 , H05B33/0845 , H05B33/0857 , H05B37/0245 , H05B37/0272 , Y02B20/19 , Y02B20/383
摘要: In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching regulator including switching elements to provide power to the LEDs. The light device includes a device support structure including a device connector and an LED support to support the LEDs, wherein the device connector is one end of the device support structure, and the power supply circuitry is supported by the device support structure. Other embodiments are described.
摘要翻译: 在一些实施例中,用于产生光的光装置包括发光二极管(LED)和包括至少一个开关调节器的电源电路,所述开关调节器包括用于向LED提供电力的开关元件。 所述灯装置包括:器件支撑结构,其包括器件连接器和用于支撑所述LED的LED支撑件,其中所述器件连接器是所述器件支撑结构的一端,并且所述电源电路由所述器件支撑结构支撑。 描述其他实施例。
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公开(公告)号:US07016354B2
公开(公告)日:2006-03-21
申请号:US10234489
申请日:2002-09-03
申请人: Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
发明人: Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
IPC分类号: H04L12/56
CPC分类号: H04L69/16 , H04J3/0688 , H04L69/161 , H04L69/22
摘要: In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.
摘要翻译: 一般来说,一方面,本公开描述了一种在分组处理中使用的方法。 该方法可以包括接收至少一个分组的至少一部分,并且基于至少一个分组的至少一部分,确定时钟信号以提供处理至少一个分组的处理逻辑。
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公开(公告)号:US06747474B2
公开(公告)日:2004-06-08
申请号:US09797480
申请日:2001-02-28
申请人: Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人: Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号: H03K1716
CPC分类号: H04L5/14 , H03K19/01759 , H04L25/0278 , H04L25/24
摘要: In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.
摘要翻译: 在一些实施例中,本发明涉及串联耦合的多个集成电路短截线。 所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体,用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体 电路芯片。 集成电路短截线包括耦合到第一,第二和第三导体的第一驱动器和第二驱动器,其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上,并且第二驱动器从第一导体接收信号 并将它们驱动到第三导体上。
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公开(公告)号:US06741107B2
公开(公告)日:2004-05-25
申请号:US09802584
申请日:2001-03-08
申请人: Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人: Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
IPC分类号: H03L700
CPC分类号: H03L7/0805 , H03L7/0812
摘要: A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.
摘要翻译: 描述了用于集成电路的同步时钟发生器,其中可以使用延迟锁定环路来延迟第一输入信号。 延迟电路耦合到延迟锁定环电路并且从延迟锁定环路电路接收用于延迟第二输入信号的控制电压。 第一和第二输入信号可以是互补的。
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公开(公告)号:US06536025B2
公开(公告)日:2003-03-18
申请号:US09858346
申请日:2001-05-14
申请人: Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
发明人: Joseph T. Kennedy , Shekhar Y. Borkar , Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号: G06F1750
CPC分类号: G06F13/4217
摘要: A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.
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公开(公告)号:US20130282992A1
公开(公告)日:2013-10-24
申请号:US13976582
申请日:2011-12-22
IPC分类号: G06F3/06
CPC分类号: G06F3/0604 , G06F3/0667 , G06F13/385
摘要: A storage unit may have an associated processor and storage controller. The storage controller associated with the storage unit may store a mapping of objects (i.e., data) to blocks in the storage unit. This mapping may be received from another source, such as a file system, database, or software application, among other possibilities. The processor associated with the storage unit may execute operation s on the objects stored in the storage unit.
摘要翻译: 存储单元可以具有相关联的处理器和存储控制器。 与存储单元相关联的存储控制器可以存储对象(即,数据)到存储单元中的块的映射。 该映射可以从其他来源(诸如文件系统,数据库或软件应用程序)等接收,以及其他可能性。 与存储单元相关联的处理器可以对存储在存储单元中的对象执行操作。
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公开(公告)号:US20130271091A1
公开(公告)日:2013-10-17
申请号:US13992627
申请日:2011-12-28
申请人: Shekhar Y. Borkar
发明人: Shekhar Y. Borkar
IPC分类号: H02J7/00
CPC分类号: H02J7/00 , H01G11/14 , H01M10/425 , H01M10/4264
摘要: An ultra-capacitor based energy source may replace rechargeable and conventional batteries. It may have the form factor of a conventional battery and may emulate the discharge characteristics of the replaced battery.
摘要翻译: 基于超电容器的能源可以替代可再充电和常规电池。 它可以具有常规电池的形状因子,并且可以模拟替换的电池的放电特性。
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公开(公告)号:US20080181331A1
公开(公告)日:2008-07-31
申请号:US12077987
申请日:2008-03-24
申请人: Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人: Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
CPC分类号: H04L25/4917
摘要: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
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公开(公告)号:US07171510B2
公开(公告)日:2007-01-30
申请号:US09752880
申请日:2000-12-28
申请人: Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
发明人: Matthew B. Haycock , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy
CPC分类号: G06F11/221
摘要: The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.
摘要翻译: 本发明在一个实施例中提供了一种用于非干涉地观察,回送和读取由总线和无线通信之一发送的信号而不干扰总线的电气特性而不增加总线等待时间并且不增加信号不连续性的装置,方法和装置 。 在一方面,具有触发器的缓冲器与连接到存储器总线的部件耦合,缓冲器将信号回送到可观测端口,并且诊断装置读取回送信号。 一方面,总线是具有三元逻辑电平的同时双向(SBD)总线之一,单端总线,差分总线,光耦合总线,芯片组总线,前端总线,输入/输出( I / O)总线,外设组件接口(PCI)总线和工业标准架构(ISA)总线。 在一个方面,缓冲器回波频率在500MHz之间的总线信号。 和5 GHz。 在一方面,缓冲器响应具有至少5GHz频率的总线信号。
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