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    EMBEDDED RESILIENT BUFFER
    2.
    发明申请
    EMBEDDED RESILIENT BUFFER 审中-公开
    嵌入式电阻缓冲器

    公开(公告)号：US20160232051A1

    公开(公告)日：2016-08-11

    申请号：US15132027

    申请日：2016-04-18

    申请人： Somnath Paul ,  Sriram R. Vangal

    发明人： Somnath Paul ,  Sriram R. Vangal

    IPC分类号： G06F11/07 ,  G06F13/16 ,  G06F5/06 ,  G06F11/16

    CPC分类号： G06F11/0787 ,  G06F5/065 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1407 ,  G06F11/1645 ,  G06F11/26 ,  G06F13/1673 ,  G06F13/1689 ,  G06F2205/067 ,  G11C29/003 ,  G11C29/023 ,  G11C29/028 ,  H03K19/00 ,  H04L1/00 ,  H04L2012/5681 ,  Y02D10/14

    摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

    摘要翻译： 描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

    Performance and traffic aware heterogeneous interconnection network
    3.
    发明授权
    Performance and traffic aware heterogeneous interconnection network 有权
    性能和流量感知异构互连网络

    公开(公告)号：US08379659B2

    公开(公告)日：2013-02-19

    申请号：US12748794

    申请日：2010-03-29

    申请人： Sriram R. Vangal ,  Nitin Y. Borkar ,  Zhen Fang

    发明人： Sriram R. Vangal ,  Nitin Y. Borkar ,  Zhen Fang

    IPC分类号： H04L12/54

    CPC分类号： H04L47/30 ,  H04L47/39 ,  H04L49/109 ,  H04L49/40

    摘要： In one embodiment, a method includes comparing an occupancy level of a buffer of a port of a router to a threshold, and controlling the port to operate at a first voltage and frequency based at least in part on the comparison, and at least one other port of the router is controlled to operate at a second voltage and frequency. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，一种方法包括将路由器的端口的缓冲器的占用水平与阈值进行比较，并且至少部分地基于比较来控制端口以第一电压和频率操作，以及至少一个其他 路由器的端口被控制为以第二电压和频率操作。 描述和要求保护其他实施例。

    Performing Variation-Aware Profiling And Dynamic Core Allocation For A Many-Core Processor
    4.
    发明申请
    Performing Variation-Aware Profiling And Dynamic Core Allocation For A Many-Core Processor 有权
    对多核处理器执行变化感知分析和动态核心分配

    公开(公告)号：US20120159496A1

    公开(公告)日：2012-06-21

    申请号：US12972985

    申请日：2010-12-20

    申请人： Saurabh Dighe ,  Sriram R. Vangal ,  Nitin Y. Borkar ,  Vivek K. De

    发明人： Saurabh Dighe ,  Sriram R. Vangal ,  Nitin Y. Borkar ,  Vivek K. De

    IPC分类号： G06F9/46

    CPC分类号： G06F1/3206 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/24

    摘要： In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个核心的处理器，每个核心具有自检电路，以确定相应核心的频率分布和泄漏功率分布。 反过来，调度器被耦合以接收频率分布和泄漏功率分布，并且基于频率分布和泄漏功率分布来在至少一些核上调度应用。 描述和要求保护其他实施例。

    Router to use three levels of arbitration for a crossbar channel
    5.
    发明授权
    Router to use three levels of arbitration for a crossbar channel 失效
    路由器为横梁通道使用三级仲裁

    公开(公告)号：US07657693B2

    公开(公告)日：2010-02-02

    申请号：US11905292

    申请日：2007-09-28

    申请人： Arvind Pratap Singh ,  Sriram R. Vangal ,  Yatin V. Hoskote

    发明人： Arvind Pratap Singh ,  Sriram R. Vangal ,  Yatin V. Hoskote

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

    摘要： A router is provided that includes a plurality of lanes to receive inbound data from a plurality of different input ports. The router may further include a shared crossbar channel coupled to each of the lanes and to a plurality of output ports, the crossbar channel to receive inbound data from the plurality of lanes and to provide outbound data to the plurality of output ports. Each lane may include a local lane arbiter, a global lane arbiter and a port arbiter associated with each port.

    摘要翻译： 提供了一种路由器，其包括多个通道以从多个不同的输入端口接收入站数据。 路由器还可以包括耦合到每个通道和多个输出端口的交叉开关通道，所述交叉开关通道接收来自多个通道的入站数据，并向多个输出端口提供出站数据。 每个通道可以包括本地通道仲裁器，全局通道仲裁器和与每个端口相关联的端口仲裁器。

    Leakage tolerant register file
    6.
    发明授权
    Leakage tolerant register file 失效
    漏电容量寄存器文件

    公开(公告)号：US07016239B2

    公开(公告)日：2006-03-21

    申请号：US10676985

    申请日：2003-09-30

    申请人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Sriram R. Vangal ,  Ram Krishnamurthy

    发明人： Bhaskar P. Chatterjee ,  Steven K. Hsu ,  Sriram R. Vangal ,  Ram Krishnamurthy

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C8/10

    摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.

    摘要翻译： 寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。 一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。 通过确定数据单元之一的选择来促进智能充电和浮动。

    Integrated circuit interconnect routing using double pumped circuitry
    7.
    发明授权
    Integrated circuit interconnect routing using double pumped circuitry 失效
    使用双泵浦电路的集成电路互连路由

    公开(公告)号：US06535045B1

    公开(公告)日：2003-03-18

    申请号：US09112466

    申请日：1998-07-09

    申请人： Sriram R. Vangal

    发明人： Sriram R. Vangal

    IPC分类号： H03L500

    CPC分类号： G06F13/4072

    摘要： Internal integrated circuit interconnect communication circuitry dual edge triggered latching circuits to transmit two data signals over a common interconnect line during one clock cycle. That is, one data bit is transmitted during each phase of a system clock over a common interconnect line. The latching circuits can be flip-flop circuits. An optional repeater circuit has dual edge triggered flip-flop circuits for repeating the common interconnect line signal on a second common interconnect line. A dual edge triggered latching receiver circuit splits, or decodes, the two combined incoming data signals into separate outgoing data signals.

    摘要翻译： 内部集成电路互连通信电路双边沿触发锁存电路，以在一个时钟周期内通过公共互连线传输两个数据信号。 也就是说，在公共互连线上的系统时钟的每个阶段期间发送一个数据位。 锁存电路可以是触发器电路。 可选的中继器电路具有用于在第二公共互连线上重复公共互连线信号的双边沿触发触发电路。 双边沿触发锁存接收器电路将两个组合的输入数据信号分离或解码成单独的输出数据信号。

    Storage element with switched capacitor
    8.
    发明授权
    Storage element with switched capacitor 失效
    带开关电容器的存储元件

    公开(公告)号：US06504412B1

    公开(公告)日：2003-01-07

    申请号：US09663750

    申请日：2000-09-15

    申请人： Sriram R. Vangal ,  Tanay Karnik

    发明人： Sriram R. Vangal ,  Tanay Karnik

    IPC分类号： G06F764

    CPC分类号： H03K3/013 ,  H03K3/356191

    摘要： A latch includes a pair of inverters cross-coupled between a storage node and a feedback node. A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor is coupled to the feedback node when the latch holds data and is not coupled to the feedback node when the latch is loading. The capacitor reduces the latch's susceptibility to soft errors when holding data, and does not appreciably slow the latch when data is loading. The capacitor is implemented using the gate capacitance of complementary transistors. A flip-flop includes cascaded latches, one or more of which have a switched capacitor on a feedback node.

    摘要翻译： 锁存器包括交叉耦合在存储节点和反馈节点之间的一对反相器。 电容器有条件地通过传递门耦合到反馈节点，使得当锁存器保持数据时，电容器耦合到反馈节点，并且当锁存器被加载时，电容器不耦合到反馈节点。 当保存数据时，电容会降低锁存器对软错误的敏感性，并且在数据加载时不会明显减慢锁存器的速度。 使用互补晶体管的栅极电容来实现电容器。 触发器包括级联锁存器，其中一个或多个锁存器在反馈节点上具有开关电容器。

    Performing variation-aware profiling and dynamic core allocation for a many-core processor
    10.
    发明授权
    Performing variation-aware profiling and dynamic core allocation for a many-core processor 有权
    为多核处理器执行变化感知分析和动态核心分配

    公开(公告)号：US09063730B2

    公开(公告)日：2015-06-23

    申请号：US12972985

    申请日：2010-12-20

    申请人： Saurabh Dighe ,  Sriram R. Vangal ,  Nitin Y. Borkar ,  Vivek K. De

    发明人： Saurabh Dighe ,  Sriram R. Vangal ,  Nitin Y. Borkar ,  Vivek K. De

    IPC分类号： G06F1/32 ,  G06F9/48

    CPC分类号： G06F1/3206 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/24

    摘要： In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个核心的处理器，每个核心具有自检电路，以确定相应核心的频率分布和泄漏功率分布。 反过来，调度器被耦合以接收频率分布和泄漏功率分布，并且基于频率分布和泄漏功率分布来在至少一些核上调度应用。 描述和要求保护其他实施例。