公开(公告)号：US07714820B2

公开(公告)日：2010-05-11

申请号：US10877388

申请日：2004-06-25

申请人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

发明人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

IPC分类号： G09G3/36

CPC分类号： G02F1/13458 ,  G02F1/1345

摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件 细分。

公开(公告)号：US20090243985A1

公开(公告)日：2009-10-01

申请号：US12407626

申请日：2009-03-19

申请人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

发明人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

IPC分类号： G09G3/36 ,  G02F1/1343 ,  G02F1/1333

CPC分类号： G02F1/13458 ,  G02F1/1345

摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件 细分。

公开(公告)号：US20080198283A1

公开(公告)日：2008-08-21

申请号：US12004742

申请日：2007-12-19

申请人： Yeo-Geon Yoon ,  Myung-Koo Hur ,  Sang-Ki Kwak

发明人： Yeo-Geon Yoon ,  Myung-Koo Hur ,  Sang-Ki Kwak

IPC分类号： G02F1/1343 ,  G09G3/36

CPC分类号： G09G3/3648 ,  G02F1/1345 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2310/0297

摘要： A display panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixel groups. The gate lines extend in a first direction and sequentially receive gate signals, and the data lines extend in a second direction that is substantially perpendicular to the first direction and receive data signals. Each pixel group includes first, second and third vertical pixels that extend in the second direction and are sequentially arranged in the first direction. The first to third vertical pixels are arranged horizontally and are electrically connected to three consecutive gate lines to receive gate signals, and are connected to two or fewer data lines to receive the data signals.

摘要翻译： 显示面板包括多条栅极线，多条数据线和多个像素组。 栅极线在第一方向上延伸并且顺序地接收栅极信号，并且数据线在基本上垂直于第一方向的第二方向上延伸并且接收数据信号。 每个像素组包括在第二方向上延伸并沿第一方向依次布置的第一，第二和第三垂直像素。 第一至第三垂直像素水平排列并且电连接到三个连续的栅极线以接收栅极信号，并且连接到两个或更少的数据线以接收数据信号。

公开(公告)号：US20070114531A1

公开(公告)日：2007-05-24

申请号：US11625435

申请日：2007-01-22

申请人： Myung-Koo Hur ,  Chang-Oh Jeong

发明人： Myung-Koo Hur ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295

摘要： A wire for a liquid crystal display has a dual-layered structure comprising a first layer made of molybdenum or molybdenum alloy, and a second layer made of molybdenum nitride or molybdenum alloy nitride. To manufacture the wire, a layer made of either a molybdenum or a molybdenum alloy, and another layer one of either a molybdenum nitride or molybdenum alloy nitride by using reactive sputtering method are deposited in sequence, and then patterned simultaneously. The target for reactive sputtering is made of either molybdenum or molybdenum alloy, and the molybdenum alloy comprises one selected from the group consisting of tungsten, chromium, zirconium, and nickel of the content ratio of 0.1 to less than 20 atm % of. The reactive gas mixture for reactive sputtering includes an argon gas and inflow amount of the nitrogen gas is at least 50% of argon gas, to minimize the etch rate of the molybdenum nitride layer or the molybdenum alloy nitride layer for ITO etchant.

摘要翻译： 用于液晶显示器的线具有包括由钼或钼合金制成的第一层和由氮化钼或钼合金氮化物制成的第二层的双层结构。 为了制造导线，依次沉积由钼或钼合金制成的层，以及通过使用反应溅射法的氮化钼或钼合金氮化物中的另一层，然后同时进行图案化。 反应溅射的目的是由钼或钼合金制成，钼合金包含选自钨，铬，锆和镍中的一种，其含量比例为0.1至小于20atm％。 用于反应溅射的反应性气体混合物包括氩气，并且氮气的流入量为氩气的至少50％，以最小化用于ITO蚀刻剂的氮化钼层或钼合金氮化物层的蚀刻速率。

公开(公告)号：US06946681B2

公开(公告)日：2005-09-20

申请号：US10732480

申请日：2003-12-11

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/28 ,  H01L23/482 ,  H01L29/423 ,  H01L29/49 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 μΩcm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

摘要翻译： Mo或MoW组合物层具有小于15μOggacm的低电阻率，并且使用Al合金附魔或Cr附魔蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 O 2 O 2的蚀刻气体系统 防止Mo或MoW合金层的蚀刻，以及SF 6+ + HCl（+ He）或SF 6 + Cl 2 2的蚀刻气体 >（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢的气体和选自以下的至少一种气体的蚀刻气体系统： 4，CHF 3，CHClF 2，CH 3，F和C 2 _{6 ，产生良好的TFT特性，H 2等离子体处理可进一步提高TFT特性。}

公开(公告)号：US20050030465A1

公开(公告)日：2005-02-10

申请号：US10877388

申请日：2004-06-25

申请人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

发明人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

IPC分类号： G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  H01L21/768 ,  H01L23/522 ,  H01L29/786

CPC分类号： G02F1/13458 ,  G02F1/1345

摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件 细分。

公开(公告)号：US06630688B2

公开(公告)日：2003-10-07

申请号：US09837374

申请日：2001-04-19

申请人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

发明人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

IPC分类号： H01L2904

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/53209 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/00

摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

摘要翻译： 首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。 通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层欧姆接触层。 接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。 然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。 接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06570182B2

公开(公告)日：2003-05-27

申请号：US10190494

申请日：2002-07-09

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L2904

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

公开(公告)号：US6081308A

公开(公告)日：2000-06-27

申请号：US31445

申请日：1998-02-26

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jueng-Gil Lee

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jueng-Gil Lee

IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/28 ,  H01L23/482 ,  H01L29/423 ,  H01L29/49 ,  G02F1/136 ,  G02F1/1343 ,  H01L23/48 ,  H01L29/04

CPC分类号： G02F1/1368 ,  G02F1/136286 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L2924/0002

摘要： Since Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single Mo or MoW layer can be used as a wiring by itself of large scale and high resolution liquid crystal. The Mo or MoW layer has the low resistivity of less than 15 .mu..OMEGA.cm and is etched to have a smooth taper angle using an Al etchant with Al or Al alloy. Therefore, it is possible to reduce the number of photolithography processes and to prevent a battery effect and generation of a hillock.

摘要翻译： 由于通过调整沉积压力可以沉积Mo或MoW层以便对衬底施加低应力，所以可以使用单个Mo或MoW层作为大规模和高分辨率液晶本身的布线。 Mo或MoW层具有小于15微米欧米伽厘米的低电阻率，并且使用Al或Al合金的Al蚀刻剂被蚀刻以具有平滑的锥角。 因此，可以减少光刻工艺的数量并防止电池效应和产生小丘。