公开(公告)号：US10854499B2

公开(公告)日：2020-12-01

申请号：US15643825

申请日：2017-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.

公开(公告)号：US10740531B2

公开(公告)日：2020-08-11

申请号：US15792289

申请日：2017-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Li-Chun Tien ,  Meng-Hung Shen ,  Shang-Chih Hsieh ,  Chi-Yu Lu

IPC: G06F30/394 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.

公开(公告)号：US10685162B2

公开(公告)日：2020-06-16

申请号：US16228530

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheok-Kei Lei ,  Yu-Chi Li ,  Chia-Wei Tseng ,  Zhe-Wei Jiang ,  Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

公开(公告)号：US10678977B2

公开(公告)日：2020-06-09

申请号：US16186788

申请日：2018-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mao-Wei Chiu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Chi-Yu Lu

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  H01L27/02 ,  G06F30/398 ,  H01L23/528 ,  G06F30/394 ,  G06F115/08

Abstract: A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.

公开(公告)号：US12266594B2

公开(公告)日：2025-04-01

申请号：US18517298

申请日：2023-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/48 ,  H01L21/768

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

公开(公告)号：US12073170B2

公开(公告)日：2024-08-27

申请号：US18354423

申请日：2023-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

公开(公告)号：US20230268339A1

公开(公告)日：2023-08-24

申请号：US17744160

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Chih-Yu LAI ,  Chi-Yu Lu ,  Shang-Hsuan CHIU ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0617 ,  H01L27/0218

Abstract: An integrated circuit including a first cell and a second cell. The first cell includes a first plurality of active areas that extend in a first direction and a first plurality of gates that extend in a second direction that crosses the first direction, the first cell having first cell edges defined by breaks in the first plurality of gates. The second cell includes a second plurality of active areas that extend in the first direction and a second plurality of gates that extend in the second direction, the second cell having second cell edges defined by breaks in the second plurality of gates. Each of the second plurality of active areas is larger than each of the first plurality of active areas and the first cell is adjacent the second cell such that the first cell edges align with the second cell edges.

公开(公告)号：US11704465B2

公开(公告)日：2023-07-18

申请号：US17106876

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC: G06F30/394 ,  H01L23/528 ,  H01L21/76 ,  H03K19/094 ,  H01L23/522

CPC classification number: G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

Abstract: An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.

公开(公告)号：US11675949B2

公开(公告)日：2023-06-13

申请号：US16722865

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ming Chang ,  Ruey-Wen Chang ,  Ping-Wei Wang ,  Sheng-Hsiung Wang ,  Chi-Yu Lu

IPC: H01L27/146 ,  G06F30/392 ,  H01L27/088 ,  G06F30/398 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0886 ,  H01L27/1104

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

公开(公告)号：US11637069B2

公开(公告)日：2023-04-25

申请号：US17220345

申请日：2021-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/02 ,  H01L23/528

Abstract: A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.