公开(公告)号：US11978736B2

公开(公告)日：2024-05-07

申请号：US17734379

申请日：2022-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Wang ,  Min Cao ,  Shang-Wen Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

公开(公告)号：US11854940B2

公开(公告)日：2023-12-26

申请号：US17231527

申请日：2021-04-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76897 ,  H01L21/76898

摘要： A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

公开(公告)号：US11791215B2

公开(公告)日：2023-10-17

申请号：US17870182

申请日：2022-07-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Wen Chang ,  Yi-Hsiung Lin ,  Yi-Hsun Chiu

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768

CPC分类号： H01L21/823431 ,  H01L21/76876 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

摘要： A fin field effect transistor device structure is provided. A fin field effect transistor device structure includes a first fin structure and a second fin structure on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure and the second fin structure. The fin field effect transistor device structure further includes a power rail over the spacer layer between the first fin structure and the second fin structure. In addition, the fin field effect transistor device structure includes a first contact structure covering the first fin structure and connected to the power rail.

公开(公告)号：US12033935B2

公开(公告)日：2024-07-09

申请号：US17836896

申请日：2022-06-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US20240222269A1

公开(公告)日：2024-07-04

申请号：US18604071

申请日：2024-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US11942420B2

公开(公告)日：2024-03-26

申请号：US17835281

申请日：2022-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

公开(公告)号：US20220262798A1

公开(公告)日：2022-08-18

申请号：US17734379

申请日：2022-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Wang ,  Min Cao ,  Shang-Wen Chang

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06

摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

公开(公告)号：US11764213B2

公开(公告)日：2023-09-19

申请号：US17214194

申请日：2021-03-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC分类号： H01L27/06 ,  G06F30/394 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66 ,  G06F30/392 ,  H01L23/48

CPC分类号： H01L27/0694 ,  G06F30/392 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5283 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A semiconductor device includes a substrate and a first active region on a first side of the substrate. The semiconductor device further includes a first gate structure surrounding a first portion of the first active region. The semiconductor device further includes a second active region on a second side of the substrate, wherein the second side is opposite the first side. The semiconductor device further includes a second gate structure surrounding a first portion of the second active region. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

公开(公告)号：US11735482B2

公开(公告)日：2023-08-22

申请号：US17833005

申请日：2022-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/768

CPC分类号： H01L21/823468 ,  H01L21/76802 ,  H01L21/823475 ,  H01L27/0886 ,  H01L21/76843 ,  H01L21/76871

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US20220302026A1

公开(公告)日：2022-09-22

申请号：US17835281

申请日：2022-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

摘要： A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.